I'm completely new to the world of FPGAs, and would like to get a sense of what is possible to achieve, and since I happen to have an interest in convolution reverb algorithms, I will use that example.
So given a room response of 10 seconds (i.e ~500000 samples at 44.1kHz), is it realistic to expect that the FPGA could handle the brute-force algorithm (which is basically a FIR filter with 500000 coefficients, running at 44.1kHz, in double precision floating point)?
An fft-based implementation would need less multiplications / additions, but since it's more complex, I'd like to begin with a simple example first!
It would be nice if in your answers you could describe the FIR-filter implementation, and produce a back of the envelope calculation, with the numbers for a specific FPGA so that I can follow your reasonning.
Thank you very much!