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I'm new to VHDL and I'm getting the following error when I try to compile my code:

** Error: F:\midterm night\assg 3\toplevel_design.vhd(18): near "<byte 0x93>": illegal character found in source

** Error: F:\midterm night\assg 3\toplevel_design.vhd(18): near "<byte 0x94>": illegal character found in source

** Error: F:\midterm night\assg 3\toplevel_design.vhd(18): Integer literal 0 is not of type ieee.std_logic_1164.STD_LOGIC_VECTOR.

Seems the problem is variable memory_block assignment.

library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all; 

entity mem8_16 is 
port( clk,wr_rd : in std_logic;
  din : in std_logic_vector ( 15 downto 0);
  addr : in std_logic_vector ( 2 downto 0);
  dout : out std_logic_vector (15 downto 0));
end entity;

architecture memory of mem8_16 is
  signal memory_temp :unsigned (127 downto 0);
begin 
  process(clk,wr_rd)
    variable memory_block: integer range 0 to 7;
  begin
    if (rising_edge(clk))then
      case addr is 
        when “000” => memory_block := 0;
        when “001” => memory_block := 1;
        when “010” => memory_block := 2;
        when “011” => memory_block := 3;
        when “100” => memory_block := 4;
        when “101” => memory_block := 5;
        when “110” => memory_block := 6;
        when “111” => memory_block := 7; 
      end case;
      if (wr_rd ='1') then 
        memory_temp((memory_block * 16 + 15) downto (memory_block * 16)) <= din (15 downto 0);
      end if;
    end if;
    dout <= memory_temp((memory_block * 16 + 15) downto (memory_block * 16));
end memory;
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  • \$\begingroup\$ Welcome to EE.SE! Please consider reformatting your post to ask a question. \$\endgroup\$ – Daniel Nov 13 '18 at 15:44
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The problem is that you have used some sort of word processor to create your source code, and it has inserted left- and right-double-quote characters (“ - 0x93 and ” - 0x94) rather than a proper ASCII double quote (" - 0x22) as delimiters around your string literals.

Use a code editor to edit code, and use the word processor to edit documentation.


Note also that there's no end statement for your process.

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  • \$\begingroup\$ thx alot but i still have a problem with the line memory_temp((memory_block * 16 + 15) downto (memory_block * 16)) <= din (15 downto 0); \$\endgroup\$ – m.rizk Nov 13 '18 at 15:58
  • \$\begingroup\$ What problem is that? \$\endgroup\$ – Dave Tweed Nov 13 '18 at 16:05
  • \$\begingroup\$ Error: F:\midterm night\assg 3\toplevel_design.vhd(28): Target type ieee.std_logic_arith.UNSIGNED in signal assignment is different from expression type ieee.std_logic_1164.STD_LOGIC_VECTOR. \$\endgroup\$ – m.rizk Nov 13 '18 at 16:08
  • \$\begingroup\$ BTW, this is awfully clunky code for creating an 8x16 memory. Why don't you use an array like everyone else does? VHDL is already extremely verbose -- why make it worse? \$\endgroup\$ – Dave Tweed Nov 13 '18 at 16:08
  • 1
    \$\begingroup\$ Exactly what it says: memory_temp is declared as unsigned. din is declared as std_logic_vector. You can't assign one to the other without some sort of conversion. But there's no reason for memory_temp to be anything other than std_logic_vector since that's what din and dout are. \$\endgroup\$ – Dave Tweed Nov 13 '18 at 16:11

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