I need to do voltage shifting (3.3V Papilio FPGA <--> 5V RAM chip).
Most of the pins are output 3.3V -> input 5V, and 3.3V qualifies as "high" to a 5V device, so I can connect them directly.
The databus is bidirectional, so that won't work - the spec sheet for the FPGA says up to 0.8V for low, and 2V to 4.1V for high; the SRAM takes less than 0.8V for low and above 2.2V for high.
I worked out this very simple voltage shifter, which seems like it would do the trick, and is within the tolerance of each device, but then I found various circuits online, and they all seem to be an order of magnitude more complicated. This says to me that there is something wrong with my design, but I can't figure out what.
This either makes a voltage divider between +5V and the FPGA-out, or between SRAM out and 0V.
Some experimentation with a spreadsheet shows that ratios of 2:1:15 for the 3 resistors (e.g 2MΩ, 1MΩ, 3MΩ) give numbers within the allowed tolerances (the FPGA would get 0V for low and 3.3V for high, and the SRAM would get 0.31V for low and 3.41V for high).
So what did I miss? It seems easier and cheaper than all the other examples.
The only thing I could find was that it might affect the rise & fall speed, but I couldn't follow the maths as to how much. The SRAM I have is rated at 100ns, and I hope to read/write it at 2Mhz, so I do have a little leeway. The control signals will be direct, so would end up a little ahead of the databus, which would work in my favour.