What is wrong with this voltage shifter?

Question

I need to do voltage shifting (3.3V Papilio FPGA <--> 5V RAM chip).

Most of the pins are output 3.3V -> input 5V, and 3.3V qualifies as "high" to a 5V device, so I can connect them directly.

The databus is bidirectional, so that won't work - the spec sheet for the FPGA says up to 0.8V for low, and 2V to 4.1V for high; the SRAM takes less than 0.8V for low and above 2.2V for high.

I worked out this very simple voltage shifter, which seems like it would do the trick, and is within the tolerance of each device, but then I found various circuits online, and they all seem to be an order of magnitude more complicated. This says to me that there is something wrong with my design, but I can't figure out what.

^{simulate this circuit – Schematic created using CircuitLab}

This either makes a voltage divider between +5V and the FPGA-out, or between SRAM out and 0V.

Some experimentation with a spreadsheet shows that ratios of 2:1:15 for the 3 resistors (e.g 2MΩ, 1MΩ, 3MΩ) give numbers within the allowed tolerances (the FPGA would get 0V for low and 3.3V for high, and the SRAM would get 0.31V for low and 3.41V for high).

So what did I miss? It seems easier and cheaper than all the other examples.

The only thing I could find was that it might affect the rise & fall speed, but I couldn't follow the maths as to how much. The SRAM I have is rated at 100ns, and I hope to read/write it at 2Mhz, so I do have a little leeway. The control signals will be direct, so would end up a little ahead of the databus, which would work in my favour.

Answer 1

If you look at the Xilinx data sheet, you can see that the input current per pin could be 10 - 15 uA. So you would have to use a resistor divider network with much lower values, which would in turn mean that you would require more power.

As far as rise time goes, the same thing applies. The input capacitance is 10 pF, plus whatever capacitance is associated with your board layout and other devices on the trace. So your RC time constant for the output impedance of your network with the input plus stray capacitance is going to be in the microsecond range, making the rise time unacceptable for a 2 MHz write speed.

Answer 2

Your overall approach is completely, umm... unrealistic. Simply put, "voltage dividers" especially in megaOhm range on a 100-ns bus is completely wrong. Pin/wire capacitances are 5-15pF, which will bring you into 10-us area. The entire approach is wrong.

First, get rid of 5-V RAM, there is no more 5-V signaling in modern electronics. You won't gain anything by using 5-V digital ICs, this is a blast from 30-years past. No one will look at this as any achievement of yours.

If you want to learn about level translation (there are cases when people need to translate 1.8V to 2.5 or 3.3V), then there there are whole families of integrated circuits that do this job. They are not that complicated.

Get at least 3.3V SRAM chips, from ISSI or Cypress for example. Then the problem of interface to FPGA goes away naturally, since FPGA I/O buffers are configurable to pretty much any interface level and type.

Also, if you would open up and post the exact type of "5V SRAM", things could be easier. Chances are that you misinterpreted the datasheets, and you might need no level translation at all.

AMPLIFICATION: It appears that the RAM in question is HITACHI HM628128ALP-10 chip. The datasheet states "Directly TTL compatible All inputs and outputs"

This appnote from Analog Devices elaborates on logic levels, stating that TTL and CMOS-3-3 are level-compatible (0.8v Low, 2.4V High):

Therefore there is no need in level translators to interface this memory chip to Spartan-3 FPGA.