The way the phase accumulator works in Direct Digital Synthesis is that every clock cycle on fclk, the frequency tuning word is added to the phase register.
For example, assume the phase register starts at 0 and the frequency word is 5.
After the first fclk pulse the phase register become equal to 5. After the second clock pulse, the phase register becomes 10. This continues for every clock pulse
The size of the phase register and tuning word depends on the size of Sine ROM and the accuracy you need to achieve in your waveform. Larger register will have more accuracy in determining the frequency that you can run at.
Here is a link to a datasheet for a DDS integrated circuit. Page 11 and 12 go into the theory of how they work.