# MOSFET driver circuit configuration for half bridge MOSFETs for power amplifier

I am making a class D audio amplifier and I am using a MOSFET driver to control two MOSFETs in a half bridge configuration as shown in the circuit below

When I connected the circuit without the MOSFET half-bridge, I grounded Vs and I got a neat output according to my needs 15 V peak at HO & LO, The problems started when I connected the MOSFETs, The HO & LO terminals started sending out the same signal but with a max voltage of 3 V or probably less, then the circuit drew around 1 AMP from my voltage source and burned the MOSFET driver chip, I knew for sure that it was burned because the resistance between the VDD terminal and the COM terminal was 26 Ohms instead of the high resistance a new chip had. An engineer in my uni suggested that the problem might be caused because I was providing the 15 volts to the MOSFETs from the same node that supplies the same voltage 15 V to my entire circuit, although my circuit was drawing only 40 milliamps from the power supply before connecting the MOSFETs.

I would like to note that the chip is FAN7390. I have fried two so far. I would guess that the common power supply might be the problem?, or it might be that the switching frequency of 125kHz the problem? The Hin and Lin signals are PWM signals with 15 V peak.

Several things wrong with that design!

• Where is the decoupling? That 15V line needs a whole pile of cap on it....
• C4???! 22uF for a boost cap, just insane, get rid of it, the 220n should be fine on its own.
• R13/14 1k, try more like 100k.
• Those mosfets, 140nC maximum gate charge?! Yea they are very, very butch fets, but you really want something much smaller and with a very much lower Qg.
• Layout? It really, really matters.
• Not the cause of the blowup, but R11/12 seem very high in value, especially given the Qg of those mosfets.
• Hello, Thanks for the answer. I have spotted another mistake, my Hin & Lin signals are 15v peak which is 3 times the input voltage rating for that particular chip. If I may ask for a few clarifications please. for the first point, what line do you mean exactly, do you mean adding a shunt cap to the VDD terminal?, because I already have that but I forgot to include it in the schematic atm. for the 3rd point, I am really confused now because I saw someone suggesting a 10 Ohm to 100 Ohm resistance range, I might be mistaken though and he might've said KOhms. The MOSFETs were available at ... Nov 14 '18 at 20:57
• ... the lab and tbh the only thing I was concerned about was the current rating, it's my first ever electronic project and my Instructor only asked us to do a simple amplification of an audio signal in base band, but I found it as an oppurtunity to use uni's resources to learn more I guess. for the 5th point, what do you mean exactly by 'layout'. as for the last point, I know that the purpose of the diode-resistor thing is to do make the gate capacitance charge discharge faster thus creating a time delay so both MOSFETs won't work together, but I really don't know what are the ranges. Nov 14 '18 at 21:01
• Does using a voltage regulator will help me solve the power distrubution issue? for example the LM7805. Nov 14 '18 at 21:14
• That is a logic level mosfet, Vgs(max) is rather low at 16V if you are using a 15V rail, and Qg is not all that much lower (a little under half what you had), I would probably use something like a STP16NF06L but there are many others, Qg about 10% of that monster you picked out. Breadboarding power circuits nearly never works, dead bug it on a bit of copper clad as a ground plane, much more likely to work. Forget the professors (mostly useless people for this kind of thing), it is the lab technicians you need to be seeking the advice of, they usually know the practise. Nov 14 '18 at 23:54
• I would not worry too much about not knowing how to do this right at graduation, nearly nobody does unless they have been a hobbyist for years before going to uni. That is what the greybeard at your first job teaches you, uni is for the theory and (especially) lots of hardcore maths, actual design chops build on what you learn at university (And very seldom involve calculating ANYTHING to three sig. fig.). High Qg means lots of switching losses and slow switching (And may explain your low gate drive voltages). Nov 15 '18 at 0:01