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I need to make an on-board SPI bus with one master and a few slave devices(microSD card, Gyroscope, magnetic field sensor). Since it is the first time for me to use more than one slave device, I wanted to know what I should be careful about.

From my understanding of the SPI interface, it is okay that the slaves have different clock polarity/phase, different data frame format(LSB/MSB first, bit-width). It would be also fine that one uses SS signal pulse in between packets, while others don't use that. Here I assumed that the master device(a MCU) changes its configuration before starting the communication with each of the slaves. Also the switching between the slaves does not have to be fast.

As far as I determine the logic level, number of lines(full-duplex/half-duplex), then I don't have to worry about other parameters in the bus configuration. Could one please confirm if this is correct?

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You are basically correct, however you are missing a couple important points:

  1. you need to make sure that each device unequivocally knows that it is the one being addressed.

  2. You need to understand exactly how each device reacts to bus activity.

For (1) you normally have individual chip selects to each device. That way there is no confusion. If the devices rely on other method of selection, you can have unintended consequences and you have to rule those out.

For (2) some devices can do things just based on bus activity. For example, some ADCs clear their data ready interrupt signal when they see a clock edge on the SPI bus. Regardless of the state of selection.

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YES.

It should be absolutely fine to use different configurations on the SPI bus with different parameters of clock polarity and need to asserting SS line for different slave devices.

Firmware overhead will increase to accommodate reconfiguration of SPI module of MCU.

If it fits your timing requirements for switching between two different slave devices, it is fine. Also, monitor your signal integrity on SPI lines when you have multiple slave devices.

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