I am simulating the Soft LVDS IP core as receiver by passing a bit stream with IP core parameters configured as follows:
Power Supply Mode: Dual (for 10M50DAF484C7G)
Functional mode: RX
Number of Channels: 1
SERDES factor: 8
Data rate: 200 Mbps
Inclock frequency: 200 MHz (This value was selected automatically after I entered Data rate)
Enable pll_areset port: checked
Register outputs: checked
In the test bench I am continuously passing a bit stream (consisting 0xAA in a loop) after
asserting the pll_areset for at least 10ns. checking if rx_locked has been asserted. but the deserialized output is not consistent with the serial input. I have tried increasing the rx_inclock frequency to 400 MHz, 800 MHz and 1600 MHz but to no avail. Any ideas what could be the issue? Besides does anyone know how the inclock frequency is calculated from the data rate? I also tried other input sequences but didn't get the same data at output. I am not sure if the SERDES IP core is either skipping bits or the word/byte boundary is misplaced. Would appreciate any help also if somebody could explain bitslip phenomenon. Thanks
Note (Added 19 Nov, 2018): The device being used is Altera's MAX10 and the IP core is "Soft LVDS".
`timescale 1 ns / 1 fs module LVDS_Test_4_tb; integer i = 0; reg clk; reg rx_in; reg [256:0] input_bitstream; reg pll_areset; reg rx_data_align; //reg align_data; wire [7:0] rx_out; wire outclock; wire rx_locked; initial begin clk = 1'b0; // align_data = 1'b0; rx_in = 1'b0; rx_data_align = 1'b0; input_bitstream = 256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000; input_bitstream = 256'hAAAAAAAAAAAAAAAA_AAAAAAAAAAAAAAAA_AAAAAAAAAAAAAAAA_AAAAAAAAAAAAAAAA; pll_areset = 1'b0; //#10 pll_areset = 1'b1; //#20 pll_areset = 1'b0; end always @ (*) begin #2.5 clk <= ~clk; end always @ (posedge clk) begin if (rx_locked) begin rx_in <= input_bitstream[i]; if (i >= 12'h100) i = 0; else i <= i + 1'b1; end end LVDS_Test_4 lvds ( .rx_inclock (clk), // rx_inclock.rx_inclock .rx_outclock (outclock), // rx_outclock.rx_outclock .pll_areset (pll_areset), // pll_areset.pll_areset .rx_in (rx_in), // rx_in.rx_in .rx_out (rx_out), .rx_locked (rx_locked) //, // .rx_data_align (rx_data_align) ); endmodule
Update: (24 Nov, 2018) So, I changed the testbench design, instead of an always block based on the posedge of data clock, now the serial data is transmitted using a forever loop in an initial block at the same frequency. This change somehow fixes the issue but partially, so I do like to understand why it behaves so? A data stream comprising 8'b11001100 was transmitted as shown in the following figure. Post-link training the data was aligned.