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I'm trying to debug some issues in an old (early-90's is old now, isn't it?) circuit, and noticed something in at least two different chip's truth-tables, and thought I'd ask here..

In the 74LS74 (Positive Edge-Triggered Flip-Flop) and the 74LS374 (Edge-Triggered Latch) datasheets, there are truth tables, showing in summary how data inputs are latched to output when the CLK input rises.

The truth-table then shows the status of the outputs when the CLK is driven low.

However, looking at this old design, it looks like the original designers are holding the CLK high; not low. There's nothing in the truth-table and no mention (that I've found) in the datasheets about what to expect when the CLK is held high. (Is it safe to assume, since it's NOT a rising edge, the outputs are already latched and will hold, just like if the CLK was low?

Edit to add, per comment: I was looking at copies of the TI sheets for both the chips above. ONE of the chips I got another vendor's sheet - and realized it was just a word-for-word copy of the Ti sheet I had, formatted differently.

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  • \$\begingroup\$ Many 74xx ICs were/are multi-sourced, i.e. there might be multiple different vendors with different datasheets for the 74LS74; can you link to exactly the one you're looking at, please? \$\endgroup\$
    – Marcus Müller
    Nov 15, 2018 at 14:24
  • \$\begingroup\$ @MarcusMüller .. Good point. Added the info. Was using Ti sheets at the time. \$\endgroup\$
    – Coyttl
    Nov 15, 2018 at 18:09
  • \$\begingroup\$ Marcus meant add an Internet hyperlink. \$\endgroup\$
    – Transistor
    Nov 15, 2018 at 18:16

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Using the TI datasheet sdls119.pdf description section (sheet 1) and schematic analysis on sheet 3, if the clock is high or low the D input is ignored.

BTW the TI datasheet is the only one so far that I've found that doesn't explicitly mention this, old Motorola and Fairchild datasheets specifically say once the clock is high or low the outputs are frozen.

If outputs follow a static "clock" signal then it's referred to as a transparent latch.

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  • \$\begingroup\$ Interesting, appreciated! If that's the case - and I have no reason not to believe you - then they knew this when designing the circuit as well, and planned on it. \$\endgroup\$
    – Coyttl
    Nov 15, 2018 at 18:11

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