I'm trying to debug some issues in an old (early-90's is old now, isn't it?) circuit, and noticed something in at least two different chip's truth-tables, and thought I'd ask here..
In the 74LS74 (Positive Edge-Triggered Flip-Flop) and the 74LS374 (Edge-Triggered Latch) datasheets, there are truth tables, showing in summary how data inputs are latched to output when the CLK input rises.
The truth-table then shows the status of the outputs when the CLK is driven low.
However, looking at this old design, it looks like the original designers are holding the CLK high; not low. There's nothing in the truth-table and no mention (that I've found) in the datasheets about what to expect when the CLK is held high. (Is it safe to assume, since it's NOT a rising edge, the outputs are already latched and will hold, just like if the CLK was low?
Edit to add, per comment: I was looking at copies of the TI sheets for both the chips above. ONE of the chips I got another vendor's sheet - and realized it was just a word-for-word copy of the Ti sheet I had, formatted differently.