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I am designing a 6-layer board, with stackup like this:

1-TOP slow North/South
2-GND
3-Signal high speed East/West
4-Signal high speed North/South
5-VDD
6-Bottom slow East/West

PCB plane spacing is:

Layer1
- 4 mil -
Layer2
- 20 mil -
Layer3
- 4 mil -
Layer4
- 20 mil -
Layer5
- 4 mil -
Layer6

I'd like to take advantage of interplane capacitance and pour alternating GND and VDD pours. However, I am not sure how this will work in regards to maintaining a proper reference plane, as the reference plane will have to switch when moving from layer 3 to 4 for example, because the layer 3 pour will block the intial layer 2 reference.

Here is an example I threw together. Brown is GND, Blue is VDD, and Pink is the signal in question

Layer 1 VDD
Layer 1
Layer 2 GND
Layer 2
Layer 3 VDD
Layer 3
Layer 4 GND
Layer 4
Layer 5 VDD
Layer 5
Layer 6 GND
Layer 6
Non poured view
Non poured view

Is this a bad idea, or do I need to stitch vias everywhere to do this? Or will interplane capacitance take care of plane switching?

The circuits on my board I am concerned about are ethernet RMII, and QSPI signals clocked at 50mhz.

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  • \$\begingroup\$ There is no need to use 6 layers for 50 Mhz. The first PC Clones are at 133 Mhz and they use 4 layers, for example. \$\endgroup\$ – José Manuel Ramos Nov 16 '18 at 8:29
  • \$\begingroup\$ Circuit density and 500mhz arm require it. \$\endgroup\$ – Erik Friesen Nov 16 '18 at 12:52
  • \$\begingroup\$ You told 50 Mhz, not 500 \$\endgroup\$ – José Manuel Ramos Nov 16 '18 at 13:47
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Put stitching vias near the signal transition vias. It would help to sprinkle some 0.01uf to 0.1uf caps between VDD and GND. 50 MHz isn't terribly fast, but it is the rise time that matters.

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