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I've had some weird occurances in labs etc. (using Cadence) where sometimes we would be told to connect the body/bulk/substrate terminal of our NMOS devices to the most negative part of the circuit (ground) and sometimes we were told to connect the body/bulk/substrate terminal to the source?

Which is it and why? I can recall it did change my circuit simulation results too by a bit. Also, I have the same question for a PMOS (connect to Vdd(most positive part in circuit) or to source?)??

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  • \$\begingroup\$ I think it depends on the circuit. \$\endgroup\$
    – nidhin
    Nov 15 '18 at 19:39
  • \$\begingroup\$ It relates to the body effect. I wish I could explain it, but I don't understand it well myself. \$\endgroup\$
    – Annie
    Nov 15 '18 at 20:13
  • \$\begingroup\$ Body effect can hugely increase the threshold voltage. \$\endgroup\$ Nov 16 '18 at 4:21
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Although in most situations (particularly in instructional settings) this is ignored, FETs are a four-terminal device. The substrate/body of the device acts as a second gate that influences the device behavior. In traditional material this is referred to as the body effect and there are equations to account for how it modifies other device parameters such as the threshold voltage, connecting the substrate to the source is the easiest way to get rid of these equations. In some non-traditional circuit designs this second gate is used to provide additional functionality. E.g., as a lower-gain input to increase the linear range of the circuitry.

In most applications this body terminal must be kept at a potential that guarantees that the drain-body and source-body diodes are kept reverse-biased so that the device can function as a FET. In most cases this can be guaranteed by connecting the body junction to the source, this creates a reverse-polarized drain-source diode. In some power applications, this diode is part of the circuit design and power-FETs include this diode characteristics as part of the available design parameters. In other power applications, such as battery-backup circuitry where reverse polarities are normal, the substrate is actually connected to the effective drain terminal of the FETs.

However, in most IC technologies the substrate itself is the body of the integrated FETs. P-doped wafers are used as a substrate over which NFETs are built. This means that there is only one substrate node for all of the NFETs in the the whole IC. The only way to ensure that the NFET diodes are kept reverse-polarized is to connect the substrate of the IC to the lowest potential in the whole circuit.

For PFETs (which reside in separate N-wells), and in technologies in which both N-wells and P-wells are available, the reason is more about better use of the available space. Connecting the substrate node of such FETs to a different potential, means that the wells have to be kept separated by relatively large distances (the related parasitic devices could destroy the IC otherwise) and that different well contact regions have to be provided. This is done for some designs, but it is better avoided for space efficiency and reliability.

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