Consider the tri-state NAND below (i.e. if EN is high, output is NAND of A&B; if EN low, output is floating. Assume EN and ~EN always track). Show work.

a) Label each transistor with a size which would allow the circuit to source or sink a minimum of 4 times as much current as a minimum sized conventional inverter through its output Y.

I dont know how to know how to get the sink or source, is there a formula for that? like if the size (W/L) = 2, then what is the current?, would size = 4 double the current of size 2?

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  • \$\begingroup\$ I dont know how to know how to get the sink or source current, is there a formula for that? like if the size (W/L) = 2, then what is the current?, would size = 4 double the current of size 2 or vice versa? I know that size of the Ptype is usually double the size of n-type \$\endgroup\$ – Jose Luis Montalvo Ferreiro Nov 16 '18 at 0:28

For a problem like this, you need to look at the worst case scenarios. For example, when sinking current, the three transistors from below the output Y, need to be on. In that case, there are 3 on resistances associated with the NMOS.

A conventional inverter looks like this:

enter image description here

Reference: http://vlab.amrita.edu/index.php?sub=59&brch=165&sim=901&cnt=1

Say the W/L for the inverter NMOS is 'n'. As you can see, for a conventional inverter, you only have a single NMOS transistor pulling low the output whereas in your circuit, you have 3. So if the NMOS transistors have the same W/L (and are matched), you have 3 times as much on resistance in your circuit.

That is what you want to address. It turns out that the W/L ratio is inversely proportional to the on-resistance of the transistors. Something like:

$$R_{on} \propto \dfrac{1}{W/L} \tag1$$

Or equivalently

$$R_{on} \propto \dfrac{L}{W} \tag2$$

So by increasing the width, for a fixed length, you can reduce the on-resistance. You want the 3 transistors (NMOS) in the pulldown side, to combine in such a way that they have the 4 times less on-resistance than in the case in the inverter.

We said that the W/L ratio in the conventional inverter case was 'n', so you want your 3 NMOS to combine to this:

$$\dfrac{1}{4n}=\dfrac{1}{x}+ \dfrac{1}{x}+\dfrac{1}{x}$$

Where 'x' is the unknown W/L for the NMOS in the pulldown network. They add up because they are in series. With that, you find:

$$x=12\cdot n $$

So you need to size these 3 NMOS 12 times the size of the transistor used in the conventional inverter. This will allow for 4 times the current capability.

You can do the same thing for the pullup network composed of PMOS. In your circuit, however, the worst case sceneario happens when one of the top two transistors (the ones in parallel) are ON and the one with the complemented EN is ON too, so you have two on-resistances to worry about. Again in the conventional inverter you only have one.

Say that the W/L ratio for the PMOS in the conventional inverter is 'p'. Since you have two transistors on when sourcing current in the worst case you need to adjust their W/L ratio i such a way that:

$$\dfrac{1}{4p}=\dfrac{1}{y}+ \dfrac{1}{y} $$

Which results in:

$$y=8\cdot p $$

So you need to size the PMOS to have 8 times the W/L of the PMOS in the conventional inverter to achieve a current capability 4 times greater.

In general, when the transistors are in series, think of it as adding more length 'L' which according to equation (2), means that the on resistance will go up. To counteract that, you need to correspondingly add more width.

When the transistors are in parallel, you could think of it as adding more 'W', which results in lower on-resistance as per equation (2).

In your circuit when all three PMOS in the pullup circuit are ON, you could in fact source more than 4 times the current a conventional inverter would (because the two transistors in parallel combine for half on resistance), but you have to design for the worst case scenario, which happens when two of the transistors are ON in the pullup branch.

Hope it helps.


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