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I have some systemverilog codes built by other colleagues and running in hardware without problem.

I can see there are some connections for two modules have no local signal declaration like this:

module module_top (
  input clk,
  input rst,
  output result
);

logic[255:0] data;  // connector for data
logic[4:0]   empty; // connector for empty
// there are no connectors for vld, sop and eop signals

module_to to (
.clk(clk),
.rst(rst),
.in_vld(vld),
.in_sop(sop),
.in_eop(eop),
.in_data(data),
.in_empty(empty),
);

module_from from (
.clk(clk),
.rst(rst),
.out_vld(vld),
.out_sop(sop),
.out_eop(eop),
.out_data(data),
.out_empty(empty),
);

endmodule

The code above can be compiled without error and running smooth in hardware.

I tried to remove the data[255:0] declaration. It doesn't work in hardware. So, please advise the theory behind it.

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3
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Verilog was invented for lazy engineers who do not like to type.

Verilog creates implicit 1-bit net declarations on port connections if you have not explicitly declared them beforehand. See section 6.10 Implicit Declarations in the 1800-2017 LRM

You can turn off this feature using the complier directive

`default_nettype none
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