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Wouldn't it be faster if there were multiple data lines (say 8) to transmit/receive data (say sequential bytes) instead of using a single line to transmit sequential bits?

marked as duplicate by Dwayne Reid, RoyC, Nick Alexeev Nov 17 at 17:07

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    It would be far more difficult to make it run at high speeds using multiple wires. There's a good reason behind it, but writing an answer that explains why would take too long - and I'm probably not the best person to explain it. – JRE Nov 16 at 12:20
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    That's how USB type C is set up. With multiple data lines. – ratchet freak Nov 16 at 16:44
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    @ratchetfreak I believe you don't even have to go that far, USB 3.0 has 4 data lines instead of 2. – Neinstein Nov 16 at 17:28
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    I feel like a lot of these responses are responding as though USB has 1 transmit wire, and 1 receive wire, when instead it has a single differential pair. Both sides both transmit and receive are on that differential pair. That distinguishes it from at least SATA. – Jay Kominek Nov 16 at 23:49
up vote 33 down vote accepted

It would be faster indeed if instead of one line you'd feed multiple lines at the same symbol clock.

But, USB's primary and foremost goal is to provide easy, serial (hence the S in USB) interfacing between low-cost devices (hence the U in USB) with low-cost, lightweight cabling.

So, that's why USB doesn't do parallel data lines: It's simply not the niche it's supposed to fill.

Also, don't neglect that having multiple high-speed parallel lanes requires the transceiver system to introduce a relative high amount of effort to compensate different skews on different lines, which at high rates are inevitable.

It's often become cheaper to make something work twice as fast than building two of the slower variant, unless you're really directly talking to hardware that is in its raw principle bit-parallel (e.g. DDR memory chips).

  • Could you explain how U in USB is related to "low cost devices"? – gnasher729 Nov 17 at 15:33
  • USB =**universal** serial bus. With "universal" was meant that it was designed to be the low-cost bus for all kind of low-cost computer peripherals. – Marcus Müller Nov 17 at 15:34

While the answer of Marcus is 100% correct, I want to add that USB 3.2 Gen 1x2 and Gen 2x2 are using two data lanes in each direction while the lanes still run at 5Gbit/s resp. 10Gbit/s each.

One of the main hurdles with any type of parallel bus is skew. If you have 8 separate wires all carrying data, it is important that all of the bits arrive at the approximately the same time. Otherwise, the bits of Byte A could get mixed up with the bits of Byte B. This means that the length of those parallel wires must be matched, within some percentage of the clock speed, so that the travel time of the signal down the wire is approximately the same. The faster the clock speed, the tighter the tolerance on the length between parallel wires.

On a PCB design for something like a motherboard, very tight design constraints are commonplace. PCB traces can achieve 1 mil or better length matching, which is good enough to implement high speed parallel interfaces. One common example of this is the DDR memory interface. This interface relies on parallel communication to move data at very high rates, but it's only possible to (affordably) implement these interfaces internally.

Imagine trying to build an external computer cable with 30+ wire connections, all length matched within a thousandth of an inch! Those cables would be very expensive compared to USB cabling.

Older computers did use a Parallel Port, which had 8 data lines but could only achieve a data rate of around 2.5 MB/s. Compare that to the 60 MB/s of USB 2.0, let alone the newer flavors of USB.

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    You can actually work around that with link training over multiple lanes, and it is done even on typically PCB-bound links like PCIe – but it really only pays to do that if you save yourself a lot of trouble by going through that amount of trouble. – Marcus Müller Nov 16 at 14:28
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    PCIe is actually a serial connection which only uses one differential pair of lines for Rx and another pair for Tx. The multiple PCIe lanes are not parallel signal lines. They only need synchronization based on the frames transmitted on it, not the digital signals. There was a discussion about this question on Electrical Engineering a couple of weeks ago. – Jörg W Mittag Nov 16 at 14:52
  • good catch, updated – Chris Fernandez Nov 16 at 14:55
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USB doesn't have Rx & Tx lines. It has one pair of differential lines, similar to RS485, with the data & clock signal encoded together. The sender sends data one way using both wires, and the receiver sends data back the other way using both lines.

Otherwise, yes, a parallel bus of signals can be very fast. Best for short distances for the reasons mentioned already.

Example of a USB data transfer:

enter image description here

As pointed out in other answers,

  • You are right, If you use twice as many lanes, you get twice the speed.
  • Earlier, parallel busses (with many data lanes) were widespread. Examples are the parallel printer interface, PATA, and PCI. But it is hard to build fast parallel busses because differences in the lengths of individual wires will cause timing differences. Parallel busses are still in widespread use on PCBs (DRAM, QSPI, GMII, ...) and on chips (AXI, AHB, QPI, ...), but for longer distances, it is actually much cheaper to build a high-speed serial link than a lower-speed parallel link with the same data throughput. Modern super-high-speed, longer-distance data links such as Gigabit Ethernet, PCIe and USB3 do have multiple data lanes, but each of those lanes is a completely independent high-speed serial link; the data streams from the individual links are combined back together at a later point. This is why you can put a PCIe x16 graphics card into a PCIe x1 slot with a fitting adapter (or sufficient violence).
  • Parallel busses have more wires (duh), so cable will be thicker and heavier and more expensive, and the connector as well.

Historically, when USB was designed, high-speed data transfer was not its main focus. The main focus was to create a universal and cheap bus system for connecting peripherals like keyboards, mouses and printers. A parallel design would have been a bad choice; it would have ruined the revolutionary small connector size and probably increased the cost of USB enough to prevent its widespread adaption.

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