Hi I'm trying to implement a counter with external control. I'm kinda new to VHDL and I keep getting syntax error for the following code. Can someone help me understand why there's an error here?
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity lab5 is
Port ( Abbreviate : in STD_LOGIC;
Halt : in STD_LOGIC;
clk : in STD_LOGIC;
LED_left : out STD_LOGIC_VECTOR(7 downto 0);
LED_right : out STD_LOGIC_VECTOR(7 downto 0));
end lab5;
architecture Behavioral of lab5 is
type State_type is (two, three, one, six, zero, seven);
signal state : State_type;
signal state_right : State_type;
signal first_time : integer := 1;
state <= two;
state_right <= six;
begin
process(clk)
begin
if (rising_edge(Abbreviate)) then
first_time <= '1';
end if;
if(rising_edge(clk)) then
case state is
when two =>
if (Halt = '1') then
state <= two;
LED_left <= "1111001";
else
state <= three;
LED_left <= "1101101";
end if;
when three =>
if (Halt = '1') then
state <= three;
LED_left <= "1101101";
else
state <= one;
LED_left <= "0100100";
end if;
when one =>
if (Halt = '1') then
state <= one;
LED_left <= "0100100";
else
state <= six;
LED_left <= "1011111";
end if;
when six =>
if (Halt = '1') then
state <= six;
LED_left <= "1011111";
else
state <= zero;
LED_left <= "1111110";
end if;
when zero =>
if (Halt = '1') then
state <= zero;
LED_left <= "1111110";
else
state <= two;
LED_left <= "1111001";
end if;
end case
end if;
case state_right is
when six
if (Abbreviate = '1') then
if (first_time = '1') then
if (state = two) then
state_right <= six;
LED_right <='1011111';
first_time <= '0';
end if;
else
state_right <= seven;
LED_right <='1100100';
end if;
else
state_right <= six;
LED_right <= '1011111';
end if
when seven
state_right <= six
LED_right <= '1011111';
end if
end process
end Behavioral;
The errors are at line 45 and it says syntax error near "state" and line 103 which says syntax error near "end"
Thank you in advance for helping out.