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I'm looking over the results from a lab I did in an introductory electronics class, and found something I'm unable to explain.

We measured the rise and fall times for two logic gates in this absolute value circuit:

  • The XOR gate in HA3 (U3,11)
  • The AND gate in HA2 (U2,10)

The results were as follows:

$$\begin{array}{|c|c|c|} \hline \ & \bf{Rise} & \bf{Fall} \\ \hline \ \bf{XOR}& 44.8 & 64.0 \\ \ \bf{AND}& 51.2 & 19.2 \\ \hline \end{array}$$

This raises the following issues:

  1. According to the datasheets (XOR, AND), \$t_{TLH} \$ should equal \$ t_{THL} \$ (typical value: 100 ns), which is evidently not the case for either of the gates (and dramatically so for AND).

  2. Following on from the first question, why is the difference in the transition time reversed between the two gates?

  3. The load capacitance should be slightly lower for the AND gate, as the path taken is shorter (with one gate less). This seems to be the case for the rise time, but not for the fall time. Why?

At first I though that the explanation would lie in differences in the capacitive loads impacting each of the gates differently. However, the load capacitance-transition time relationship should be pretty much the same (figures 6 and 12 in the XOR and AND gate datasheets, respectively).

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The "typical" timing values given in the datasheet are usually not very helpful. You should be looking at the maximum timing values. Furthermore, the data sheet is not saying that the rise and fall time are the same...it is saying that both timing values are guaranteed to be less than the specified maximum (200ns). There is also no specification that tells you that the rise time will be less than the fall time, or vice versa.

The timing values you observe in an actual circuit may also be different for the various input transitions that can cause the output to change. The delays may be different for different manufacturers, or for the same manufacturer but parts manufactured on different days. The only thing you can count on is that the observed transition times and propagation delays will not exceed the maximum specified values.

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