Is there any model for Analog Multiplexer compatible with LTSpice or Cadence Virtuoso?
A simple 2:1 multiplexer is implemented in LTSpice as a SPDT switch. So how to implement a 4:1, 8:1 or 16:1 multiplexer?
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Another solution is to use a behavioural source with
table(), such as this:
table( V(ctl), 1, V(1), 2, V(2), ... )
V(ctl) is the controlling voltage supplying various voltage levels, fixed here for clarity, and the nodes labeled as
2, etc, from which the voltages
V(2), etc, are taken are the inputs.
It's not an ideal solution because behavioural sources tend to suffer from dynamic range fidelity, especially when higher quantities are involved (hundreds of Volts and above), and temporal if the signal has a very large bandwidth. A minor solution is the two hidden parameters,
tripdt (see manual, or ltwiki), but they can only do so much.
Considering you mentioned VCSW, it should be fairly trivial to implement the switch with more than two switches, for example a complementary pair for each input, or one switch for every input, driven by logic. Not home right now but here's a very quick attempt at the 2nd suggestion:
The pink voltage is the control, the upper pane has the inputs, for comparison with the output below. I've done it so because it seemd to me you're after a behavioural attempt, not a full, real-life scenario; if that's the case, use the 4-pin MOS to build your own transmission gates, for example.
Obviously, you could build a subcircuit for a complete CMOS analog mux out of MOSFETs if you need that level of detail.
But if you're looking for a simplified behavioral model, you can base it on voltage-controlled resistors — after all, a switch contact can be thought of as a resistor that varies between, say, 1 mΩ and 1 GΩ.
Use logic gates or logic expressions that take your "select" values as input to generate the control value for each resistor in order to build an N-way multiplexer.