I have a data set consisting of 30 values and each of 16 bit wide. I tried to add these values as an input in my Verilog code in the following way:

`timescale 1ns / 1ps
module com (inp,clk,out);
input clk;
input reg [15:0] inp;//dataset
output out;

but when I am writing input reg [15:0] inp; it is showing some error.

Can anybody tell me how can I use this data set values as an input in my verilog code.

  • 1
    \$\begingroup\$ Registers simply cannot be inputs. For a register you would have to decide the condition on which it adopts a value, and write a suitable assignment expression. \$\endgroup\$ Commented Nov 18, 2018 at 15:03
  • \$\begingroup\$ actually i am using inp=0 under always block, and got some error , can you suggest me instead of always block what can i use? \$\endgroup\$
    – David
    Commented Nov 18, 2018 at 17:03
  • 1
    \$\begingroup\$ If you're assigning a value to it in this module, then it's not an input to this module. It's either an internal signal, an output, or an inout. \$\endgroup\$
    – The Photon
    Commented Nov 18, 2018 at 18:17
  • \$\begingroup\$ In my code i am using like , always @ (posedge clk); begin if(rst); begin inp=0, means if(rst) input will be zero, and error is showing like procedural assignment to a non-register inp is not permitted \$\endgroup\$
    – David
    Commented Nov 19, 2018 at 3:30
  • 2
    \$\begingroup\$ @TuhinDas - you simply cannot assign an input - that's fundamentally in contradiction with the very concept of an input. Perhaps you want to make a registered copy of an input. But that consists of having a register, and under some conditions assigning it the value of an input. \$\endgroup\$ Commented Nov 19, 2018 at 18:42

2 Answers 2


If you want to assign a value to something, then it is a register (reg). If you want to connect two things, then you need a wire. If you want to get a signal from an external block you use an input and if you want to send a signal to an external block you use an output. outputs can be wires or regs, but an input cannot be a reg. If you're trying to assign a value to inp inside your block, then how can you also say the value of inp is determined by another block?

Maybe this is more what you're trying to do: on the clock edge, if reset is high then inp_registered gets 0. Otherwise, it gets the value of inp:

module com(

input rst;
input clk;
input [15:0] inp;

reg [15:0] inp_registered;


always @(posedge clk) begin
    if (rst == 1) begin
        inp_registered = 0;
    else begin
        inp_registered = inp;

Inputs are just inputs — there's no distinction between inputs driven by wires and inputs driven by regs.


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