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I've designed a PCB schematic that uses a MOS device to switch one of the higher power rails. I've looked through the datasheets many times, and believe it should work, according to the Current-Voltage characteristics of the device. However, I'm very apprehensive about this, as I am worried that I missed something, and the drain-source voltage drop will degrade the available power on the rail.

I'm hoping someone could double check my design:

Here is the schematic: enter image description here

The regulators shown here are fixed voltage, Medium current (<5A). The MOSFETS are planned to be IRLB8743PbF NMOS. Here's the datasheet.

According to this graph in the datasheet, I believe this device should operate without a significant voltage drop on the output rail, at a Vg of ~3.3V. It is important that the drop be no more than half a volt to prevent sensor brownouts. Also, I anticipate the rails using very low current (mostly powering microcontrollers). enter image description here

I would really appreciate any personal experience tips, or any help finding stuff I may have missed in the datasheet.

Thanks in advance!

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    \$\begingroup\$ When you want to turn on the FET, what will the gate voltage be? In other words, what is the voltage of the TEL_ON signal? In order to keep it on, you will need a voltage of around 16.5V. If TEL_ON is less than 12V, the FET will remain completely switched off. \$\endgroup\$ – mkeith Nov 18 '18 at 16:53
  • \$\begingroup\$ Thanks for pointing that out, I forgot to include that. I will be using 3.3V logic high as Vg. I will edit my question to include this. \$\endgroup\$ – axwege Nov 18 '18 at 16:55
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    \$\begingroup\$ N-Channel FETs are inappropriate for your application. A P-Channel high side switch (perhaps read this: baldengineer.com/…) would be a must better design. In the circuit you show you need to increase the gate voltage ABOVE the switched voltage by the VGS drive voltage ….possible for the 3.3 and 5 volt regulators, but marginal for the 8V regulator (since the maximum drive you have is 12V). \$\endgroup\$ – Jack Creasey Nov 18 '18 at 17:06
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    \$\begingroup\$ @axwege, for a moment, just consider your desired operating condition. Vgate = 3.3V. Vdrain = 12V. Vsource = 12V. Now, in this operating condition, what is Vgs, the gate to source voltage? It is -8.7V. But if Vgs=-8.7V, then the FET will be switched fully off, because Vgs(th) is positive, not negative. Therefore, this desired operating condition is impossible. \$\endgroup\$ – mkeith Nov 18 '18 at 17:09
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    \$\begingroup\$ Consider when the FET is off. Vd = 12V, Vs=0, and Vg=0. Now, as you raise Vg from 0 up to 3.3V, the FET may begin to conduct, but only until Vs = (3.3-Vgs(th)). If Vs increases above that point, the FET will start to turn itself off again. This is called a voltage follower, because the source follows the gate voltage (less Vgs(th)). \$\endgroup\$ – mkeith Nov 18 '18 at 17:15
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You have gotten great feedback already. It's obvious that the best approach is to use a PMOS instead of the NMOS. You could use something like this, with a PMOS (and NMOS) to get what you are looking for:

schematic

simulate this circuit – Schematic created using CircuitLab

With this you can use a low voltage signal (e.g 3.3V, 5V) to turn on the PMOS. With no signal at the NMOS gate, both the NMOS and the PMOS are OFF. When you apply 3.3V at the gate of the NMOS, that will turn it ON, and will pull the gate of the PMOS down to 0V—this will turn ON the PMOS since now VG-VS (e.g -5V, -12V) is enough.

Just need to pick the two the MOSFETs. For the NMOS, something like the DMN3067LW works great (turns on with low voltage). For the PMOS, you need to pick one with the 5A current capability you want.

One caveat though, if you were to keep the same configuration as you have it, you need to pick a PMOS capable of turning on properly with 3.3V, and 5V. The 8V regulator should work fine because you have the PMOS before the regulator. So you have a high voltage signal (12V), and when you pull the gate down to 0V, VG-VS=-12, enough to turn on most high current transistors (and with lower RDS(on)).

In your 3.3V and 5V regulators, you have the PMOS, after regulation which puts the source either at 3.3V or 5V which means that pulling down the gate will have a VG-VS of either -3.3V or -5V, enough to turn on the PMOS but possibly with higher RDS(on) and at 5A that maybe a drop you would not want (plus heat). For those, I'd place the PMOS/NMOS control circuit before the regulators (just like for the 8V regulator) so that there is enough drive (approx. -12V). You could find transistors that will turn on for 3.3V or 5V but at the expense of higher RDS(on).

Hope this gives you more insight.

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Given the circuit you presented I'd suggest you can make this configuration work for both the 3.3V and 5V supplies, but you need to change to a P-FET for the 8V regulator switch.

You circuit should be something like this:

schematic

simulate this circuit – Schematic created using CircuitLab

Note that the logic for the 8V switched is opposite to the other two supplies. There is plenty of drive for the 3.3 and 5 volt switches, only the 8 volt needs a P-Channel.

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Rds(ON) of that FET is 3,2 mΩ (or 4,2 mΩ if you use 5 V Vgs instead of 10 V). With 5 A you would lose 16 mV (21 mV with 5 V Vgs). If you have any wiring, you will probably lose more voltage to those

Power dissipation is 80 mW (105 mW with 5 V Vgs) so you don't have to worry much about that.

What are you using for TEL_ON signal? You have to pull that to over 17 V for your circuit to work.

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The idea is fatally flawed. You cannot simply “choose” what region to operate in, you have to design the circuitry so that the transistor operates in that region.

While you can use an NMOS as a high-side switch, you have to provide it with a high-enough gate-source voltage for it to enter the triode region, this means that your gate drive has to be several volts above the desired supply rail.

Your highest rail seems to be 8V plus drop-out, plus threshold voltage, indicates that you would need on the order of a 13V gate drive.

Then is the issue of power dissipation, if it is not in the triode region there will be a voltage drop across the device. To avoid this you would need an auxiliary DC-DC converter that provides you with a high-enough voltage to power level shifters to provide the necessary gate drive to enter the triode region.

For all of these reasons NMOS are rarely the first device to consider as a high-side switch. PMOS are much easier to design for in this particular application. The necessary level-shifting to turn off-the device can simply be done with one or two resistors and an open-drain driver.

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At 10 volts Vgs, and 40 amps Idrain, you have 0.1 volts nominal, ignoring any heating effects. The "triode region" resistance, one way to view a FET, is R = V/I =0.1/40 = 2.5 milliOhms.

At 5 amps, the power will be I *I * R = 25 * 0.0025 = 65 milliWatts.

This looks to cause just a few degree Centigrade temperature rise, if you heatsink the FET. Is that your plan?

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Note, with the downvote, I stated the Vgs was to be +10 volts. If the OP implements that, the design is viable. Likely to be awkward, but viable.

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  • \$\begingroup\$ I do plan to heat-sink the MOS, however, I need to account for operating temperatures up to 100 degrees Celsius. \$\endgroup\$ – axwege Nov 18 '18 at 16:54
  • \$\begingroup\$ Then you need device characteristics at 100C, and nominal thermal resistance. Will this be air-cooled, or is the heat to be dumped into some chassis? \$\endgroup\$ – analogsystemsrf Nov 18 '18 at 16:56
  • \$\begingroup\$ Chassis Cooled. I will be unable to use any air cooling. \$\endgroup\$ – axwege Nov 18 '18 at 16:57
  • \$\begingroup\$ He is using NMOS as a high-side switch in a source-follower configuration with a gate voltage of 3.3V. Triode region is not even in the picture. \$\endgroup\$ – Edgar Brown Nov 18 '18 at 17:06
  • \$\begingroup\$ You are only dumping 65 milliWatts. That is about 5 degree Centigrade of thermal-gradient per square of copper. So don't be cheap with the copper foil. Keep the path short and wide. \$\endgroup\$ – analogsystemsrf Nov 18 '18 at 17:07

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