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I am trying to design a set of switches in a cmos design. The switches are supposed to control a number of capacitors and I want to implement them as single NMOS or PMOS transistors.

Based on my understanding I have done the following: Choosing PMOS for switches where the voltage signals switched are closest to VDD and NMOS for switching voltages closer to gnd, to enable optimal drive conditions and this way decrease Rds_on. All the switches are driven rail-to-rail.

I also think that I have to ensure that all the switches operate in the ohmic region.

But when it comes to wiring the body terminals I get a little bit confused. I have read that you should tie the body terminal to the source terminal/gnd in the case of NMOS. In my design, some of the switches are placed in between a PMOS sitting at the top and NMOS. In this case the source terminal is not connected to the lowest potential, should it then be wired to ground or the source terminal?

I have also heard that transistors in common design processes are symmetric devices. Does this mean that it does not matter if the drain and source terminal are swapped? Does the body potential influence this polarity?

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Usually if you want to use for example an NMOS as a switch to ground you would simply connect the body (bulk or backgate) to ground. Then source = body and things are simple, Vgs is the same as Vgb (gate-bulk voltage).

Note that when we want to operate this NMOS as a switch we want a large Vgs. In the (grounded source) example I mention above Vgs = Vgb. Now think about it, do we actually need a large Vgs or do we really just want a large Vgb?

The conductive channel in an NMOS forms when Vgb is large enough. So when the Gate to Body (bulk, substrate whatever you call it) is large enough. Would the channel still be there if I disconnect the source: yep.

So the source voltage/connection doesn't matter that much. The large Vgb is what we really want and need. So that means we should connect the Body to the lowest voltage so that Vgb becomes as large as it can be giving us the lowest on-resistance.

If you're designing this circuit to be on an IC then for the NMOS you might not even have a choice. If the NMOS are made in the "global substrate" of the silicon die than you have no choice: all NMOS Body contacts will be this "global substrate" and will be connected to ground.

Some CMOS processes do allow you to make a separate "P-well" to place your NMOS in. But even then, for reasons mentioned above it is still the most beneficial to connect the Body contacts to the lowest voltage, i.e. Ground (or VSS).

For PMOS you generally do have a choice as these are inside an "N-well". Generally this N-well needs to be connected to the highest voltage which is the supply (VDD). The Vbg and channel story also applies to the PMOS so generally you can just connect the Body to VDD.

I have also heard that transistors in common design processes are symmetric devices.

If you look at the most simple sideview of an NMOS transistor, you can see that the transistor is indeed symmetrical:

enter image description here

And in all CMOS processes the "basic" transistors are symmetrical, source and drain are the same.

Only for "special" (for example RF or High Voltage) transistors this might not be the case.

For PMOS the same is true, the "basic" PMOS transistors are symmetrical, source and drain are the same.

Does this mean that it does not matter if the drain and source terminal are swapped?

Correct.

Does the body potential influence this polarity?

No it does not, as the drain and source are physically identical structures.

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  • \$\begingroup\$ Very good explanation. As far as i understand you that means that the transistors will "dynamically" form the drain and source terminals based on the voltages applied. Having access to N-well process will give more flexiblity for some applications but in my case wishing to minimize Ron I should connect all body NMOS to gnd and PMOS body to vdd. The same principle would also apply for a switch that is operating at an intermediate voltage between the rails? Is it correct that in this case a bigger Vsb will lead to a bigger Vt and therefore Ron will suffer? \$\endgroup\$ – bubbleboy Nov 20 '18 at 13:10
  • \$\begingroup\$ Right, what is called drain and what source generally depends on the expected direction of the drain current. If that's unclear, then it does not matter as a MOS transistor is symmetrical (except the special types). Almost all CMOS processes are P-substrate with N-Well for the PMOS. The reverse: N-substrate with P-well basically does not exist as far as I know (never seen it). Yes the drain/source voltages do not matter as long as the gate voltage stays at least Vt above the drain/source voltage (for an NMOS). You already know this because you would use PMOS if the voltage gets too high. \$\endgroup\$ – Bimpelrekkie Nov 20 '18 at 13:17
  • \$\begingroup\$ Is it correct that in this case a bigger Vsb will lead to a bigger Vt and therefore Ron will suffer? Yes Ron will increase when the body is connected to one of the supply rails as the "overdrive voltage Vgt = Vgs - Vt decreases, due to Vt increasing (body effect). But there are other practical advantages to still connect body to GND/VDD, if you connect the body to source, you must be sure that the drain voltage will always be above the source voltage (for NMOS) otherwise the body-drain diode can come into forward mode. Using GND/VDD is simply more "foolproof". \$\endgroup\$ – Bimpelrekkie Nov 20 '18 at 13:36
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In the low-voltage CMOS processes I have used, there are no layout differences between Source and Drain. There are, in two high voltage processes, either required Drain implants or optional Drain implants; these implants reduce the intensity of the voltage gradients in the silicon.

If your FETs are laid out on the substrate, as would NFETs on Psubstrate, then you have no control of the behavior of the FET's backside/bulk/body. In some processes, such as twin well, both types of FETs are in tubs (one type would be in nested tubs), you do have control of the body, but at substantial increase in layout area, unless you can share the tubs.

OP requests layout details

schematic

simulate this circuit – Schematic created using CircuitLab

BLUE DOTS is the active implants for drain and source. In this layout, the DR and SRC are identical, and thus swappable.

Red Dashes is the gate structure.

Black Dashes is the metallization

Small Black Squares is the contacts from metal to active, or form metal to gate (poly here)

The BULK/BODY is off to the side.

By the way, the body-potential does not affect the swappability of these drawn-symmetric drain/source type of FETs.

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  • \$\begingroup\$ Thank you for reply. I feel that your answer is a little bit beyond my level. I have very little experience with physical layouts of transistors. I do not use twin well and wonder if you can elaborate on "no control of the behavior of the FET's body". My knowledge goes as far as knowing the devices have a body terminal in the symbol. What is the consequence of "no layout differences between Source and Drain"? What determines if something is a drain or source terminal VS using a discrete transistor? Should the body terminal of a NMOS be tied to source or gnd when source terminal is not at gnd? \$\endgroup\$ – bubbleboy Nov 20 '18 at 10:31
  • \$\begingroup\$ Show the schematic of what you want to do. If you wish to stack discrete (separately packaged) FETs, you need to rethink the system design. If body is not tied to source, then the Vthreshold becomes uncontrolled. \$\endgroup\$ – analogsystemsrf Nov 20 '18 at 11:23
  • \$\begingroup\$ I fail to see the point of this answer as it does not address the main topic of the question which is how to connect the Body of the transistors. Op clearly isn't familiar with the layout of CMOS transistors so I see no point to discuss that. \$\endgroup\$ – Bimpelrekkie Nov 20 '18 at 12:13

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