# PN sequence verifier

I have a AD9253 ADC connected to an FPGA. I want to verify the design, so I use the ADC in PN sequence short mode. (See p.28 in the datasheet.)

Here is a table (from the data sheet) which shows the 4 first output.

My problem is that I cannot create the same sequence (even the 4 first output) with my PN-sequence generator.

I have read the ITU 0.150 standard, but I didn't get the solution.

I tried to implement based on the following schematic from this document.

I like to model digital stages in Excel. Here is my solution. (Which fails.)

The time elapse from top to down, and each row shows a snapshot of the shift register. I hoped that the column I results the PN-sequence.

Cells in the first column has the feedback formula. (Eg.: A2: =IF(OR(AND(E1, NOT(I1)), AND(NOT(E1), I1)), 1, 0)) All other cells gets its value from the top left cell. (Eg.: The B2 cell formula is the following =A1)

• It's a bit confusing that they say in text, "The seed value is all 1s", but then Table 12 gives an initial value of 0x1FE0 which is only 8 1's. Can you find the place in your pattern that has an output of 0x1FE0 and see if the patterns match from there? – The Photon Nov 21 '18 at 17:53
• The standard says: Number of shift register stages: 9. I cannot treat 0x1FE0 as initial value of the generator it is too long. – betontalpfa Nov 21 '18 at 18:15
• Presumably only the 9 msb's are part of the actual shift register. But still 0x1FE0 only has 8 bits set to 1, not 9. – The Photon Nov 21 '18 at 18:35
• I have flip the LSB-MSB in my excel simulator. – betontalpfa Nov 26 '18 at 7:14

I do my modeling in Perl. The following code generates the sequence listed in the datasheet:

#!/bin/perl -w

# 14-bit words:
# | 1   F   E   0| 1   D   F   1| 3   C   C   8| 2   9   4   E|
# |01111111100000|01110111110001|11110011001000|10100101001110|

# Initialize PRNG to all-ones
my $reg = 0x1FF; for (1..8) { # Initialize 14-bit output word my$out = 0;
for (1..14) {
# Shift the next bit into the LSB of the output.
$out = ($out << 1) + !!($reg & 0x100); # Advance the PRNG to the next state: # XOR bits 4 and 8 together and shift into bit 0.$reg = (($reg&0xFF) << 1) + (!!($reg & 0x10) ^ !!($reg & 0x100)); } # In order to get the required pattern, invert the MSB of the output word printf "%04X\n",$out^0x2000;
}


The output is:

1FE0
1DF1
3CC8
294E
1479
1CD8
0A47
26D5


I'm not sure where that final inversion of the MSB is coming from, but my first attempt was correct except for that detail.

An interesting question is, how do you predict the next word when you're only given an arbitrary word in the sequence? Note that the 9 most-significant bits of the arbitrary word (after you undo the MSB inversion) are in fact identical to the state of the PRNG register at the beginning of the generation of that word.

So, if you take those 9 bits to initialize your checker, then run 14 cycles, you'll re-generate the word you started with. Then the next 14 cycles will generate the next word in the sequence.

Here is a configurable PRBS checker that should be able to check both of these patterns: https://github.com/alexforencich/verilog-lfsr/blob/master/rtl/lfsr_prbs_check.v . You may need to experiment a bit with the parameters to get it to match the pattern. I was able to get the corresponding generator https://github.com/alexforencich/verilog-lfsr/blob/master/rtl/lfsr_prbs_gen.v to generate the same sequence using the standard PRBS 9 parameters and fudging the init value until I got it aligned (normally this isn't necessary, but apparently 14 is a factor of 1022 and hence not all possible offsets are reached), except for the inverted MSB noted by Dave. Not sure what the story is with that.