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In the last few months I have been working on this project and now the next stage is to make a PCB for this circuit.

I know this PCB is very far from perfect (my first PCB), but I would like to know if this may work properly or if it does not even make sense to send to the manufacturer for production.

This circuit on the breadboard is working without problems.

I am using a microcontroller to receive GPS (will be connected to the GPS headers) coordinates from a Neo 6M module. The microcontroller will process those coordinates and will activate a relay if needed. Every 10 seconds I will read the GPS and send data from the DB9 connector (serial) over UART. The uC has a 16 MHz external crystal.

I am on a budget and I need to make this into a two layer PCB. I know that the best approach is to make a ground plane and make the data tracks on the other layer however without ground plane will this work in theory?

Can I connect the 16 MHz crystal this way or will it cause electrical noise?

By the way, any more obvious mistakes that I am making?

enter image description here enter image description here Thanks very much and sorry for the noob questions!

EDIT:
First of all thank you for all the help! Made some new changes to the design:

  • Changed footprint of 20pf and 100nf capacitors to non-polarized.

  • Added 100nF bypass cap.

  • Switched position of crystal caps and the crystal itself.

  • I managed to get a bottom ground plane to improve stability.

A few considerations:

  • Design rule check shows no errors.

  • There is really no need for mounting holes yet.

  • I use THT because this is my first PCB and to not get over my head with SMD components.

Now that I got all the GND stuff out of the way, can you tell me if I am on the right way or is it missing something ? I will optimize the board as suggested, I am just making sure I am not doing anything foolish without realizing it :)

enter image description here

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  • \$\begingroup\$ Are you sure about some of those capacitor packages? You've got polarized capacitors for all of the caps on your board, and I don't think you can even get 20pF polarized caps.. \$\endgroup\$ – Hearth Nov 22 '18 at 1:41
  • \$\begingroup\$ You might want to read this. It might give you some pointers. electronics.stackexchange.com/a/407744/202270 \$\endgroup\$ – Edgar Brown Nov 22 '18 at 1:42
  • \$\begingroup\$ Where is your ground plane? Why is everything to sparse? Where are your decoupling caps? Why though-hole? \$\endgroup\$ – winny Nov 22 '18 at 8:22
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    \$\begingroup\$ Still, most of the traces can be moved to the brown layer, so you'll get a ground plane as solid as possible. In fact, I see only a few traces (all at the ICSP header location) that really need to go through the other green layer. And if you can afford putting traces between pads (2.54mm is huge), I think you can all put them on the brown layer, with a bit of effort. \$\endgroup\$ – dim Nov 27 '18 at 13:04
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    \$\begingroup\$ If you are short on cash you should bite the bullet and do SMT components. They are cheaper, and you can have a smaller board which will be cheaper too. 0804 and 0603 sized stuff is pretty easy to hand solder. Don't be intimidated by SMT. \$\endgroup\$ – whatsisname Nov 29 '18 at 4:52
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Problems with ATmega connections:

  • You have to connect all supply lines (including AVcc even if you are not using ADC / analog to digital converter)
  • You need decoupling capacitor near ATmega supply pins

Please read this:

AVR042: AVR Hardware Design Considerations - Application note

Other problems:

  • you could make some holes for screws
  • you could optimize component locations and orientations waaay better. Board is messy, there could be only few connections on the second layer. Come on, optimize it.

For example:

  • 1N4007 diode for relay could be placed horizontally, transistor and LED in relay circuit could be closer to that diode
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  • \$\begingroup\$ +1 for the mount holes. Boards without at least three mount holes are a pest (unless there is some other obvious means of mounting.) \$\endgroup\$ – Janka Nov 22 '18 at 13:06
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  • Do a design rule check, some of your traces (e.g. that one crossing the DB9 connector) are touching pads they should not touch.
  • Use SMD components for the crystal caps.
  • Switch the position of the crystal and its caps.
  • Put a guard ring around the crystal and connect it and the caps at one single point near the µC to GND.
  • Your µC is missing a 100nF bypass cap.
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There is quite a few optimizations that you can still make.

  • The tace running from uC1 to C10 gets very close to the Crystal, try running the trace so there is good separation between the two and so the ground plane on the bottom layer can help eliminate any noise on the clock traces.
  • The trace between C3 and uC1 is on a different layer. Try keep all the clock traces on the same layer and all the same length (I know sometimes this can be hard).
  • Use your Schematic as a guide. Look at where the capacitors are placed and in general on the schematic and try replicate it. What I mean by this is look at the likes of C2, it is right next to L7802 in your schematic. However on the PCB it is floating off up the top. The capacitor would be way more effective inline on the trace between L8705 and uC1/MAX1. Same for C10 and C6. Capacitors work more effective close to the part they trying to suppress ripple from.
  • Try keep your traces at 45 degree angles, makes it look better and less chance of signal leakage corners of traces. (Traces to GPS1 need work).

Hope this helps.

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