# How to generate signal with glitches in VHDL?

I am working on an assignment in which I have to report the number of glitches in a signal.

For the testing purpose I was wondering how can I generate a signal with glitches in VHDL?

• You need to be a lot more specific. For 9600 Baud 1 MHz is a glitch, for a 3 GHZ clock it is almost DC. Nov 22 '18 at 7:00
• I meant unwanted spikes in signal. Like a digital Signal with value 1 momentarily changes to value 0 and then is back to value 1. Nov 22 '18 at 9:14

For generating test bench stimulation signals generally the code is based on using "after" or other not synthesizable keywords.

By the way, you can use the hazardous circuits for generating the glitches at the real world.

    library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity glitch is
Port ( CLK       : in  STD_LOGIC;
HazardOut : out STD_LOGIC;
);
end glitch;
-- simulate it with component delays. functional simulation
-- will not show the glitches
architecture Behavioral of glitch is
signal dly     : STD_LOGIC;
signal CLKdly  : STD_LOGIC;
begin
dly    <= not CLK;
clkdly <= not dly;
Hazardout <= CLK xor  clkdly;
end Behavioral;

• This component will add glitches each clock cycle. You may want to add a randomly based condition (using "uniform") to generate the glitch based on a comparison of the random number to a threshold. Nov 24 '18 at 4:24