I have an issue that I can't understand and looking for your help to give me some insight to solve it. I'm using a module named dw1000 that is used to measure distance using UWB at 6.4Ghz, 3.95 Ghz...etc.

The IC block diagram looks like this:

looks like this

The pins VDDPA1 and VDDPA2 on the left side of the block are used to power directly the Tx/Rx power amplifier and since the module is power hangery ( 150mA @ 3.6V) plus the noise that this amplifier generates. 3 decoupling capacitors are recommanded on each of these pins (12pF,330pF and 100nF) and they should be placed as close as possible to these pins as any decoupling capacitors.

I followed the recommanded values, placements, etc. The module has a continuous transmisison mode where the central frenquency is observed and tuned so I use this mode to check out if my device is working or not.

PCB layout of the decoupling capacitors:

PCB layout of the decoupling capacitors

First tests gave me the following RF ouput:

RF output

As you can see in the image above there is no central frequency and it's obviously very noisy.

So I put the 3 decoupling capacitors on top of each other:

on top of each other

To get them as close as possible to the pins and it did work for one board or 2 but not all.

Then I added a ferrite(BLM15AG601SN1D) on each pin just before the piled capacitors and like magic this fixed the problem in all boards.

The output signal when everything is clean and working looks like this:

looks like this

Is there an explantation for this and how can I fix it?

  • \$\begingroup\$ It seems that your 3.6V power supply is noisy. Thus it helps to block it with ferrite. \$\endgroup\$ Commented Nov 22, 2018 at 11:07
  • 1
    \$\begingroup\$ It is not 100% clear. The ferrites are between the pin and the capacitors. Right? \$\endgroup\$ Commented Nov 22, 2018 at 11:44
  • \$\begingroup\$ @StefanWyss: I'm using an LDO to convert 3.6 coming from a battery to 3.3V and I tried to power the board with an external power supply but it didn't help \$\endgroup\$
    – C.Hicham
    Commented Nov 22, 2018 at 11:52
  • \$\begingroup\$ @EdgarBrown, the ferrites are before the capacitors, then the capacitors are connected directly to the pins otherwise you'll have just a bunch of peaks after the ferrite \$\endgroup\$
    – C.Hicham
    Commented Nov 22, 2018 at 11:54
  • 1
    \$\begingroup\$ Well, the LDO itself should not introduce much noise. So I think it might be other parts of your circuit that couple noise on the RF supply. \$\endgroup\$ Commented Nov 22, 2018 at 11:57

3 Answers 3


The spectral plot shows a huge spurious at 700MHz. Get some bypassing UNDER THE package, perhaps on backside; or atop the ICs pins, with 1mm*2mm SMT cap

I'd suggest your initial circuit was an oscillator; those capacitors are not close enough, given you want a 6 GHz power amplifier to be happy/stable/good-data-eye/emit a UWB burst.

The Bead provides some loss, and quenches/dampens the parasitics.

I'd get a tiny 10pF and solder that right across the leads.

To estimate the Fresonate, assume 1nH/millimeter. Thus 6mm (plus lead frame and bondwires), for total of 10nH.

The Fresonate of 10nH and 10pF is only 500MHz, thus your onchip parasitics are part of the energy circulating path. You bead(s) provided dampening.


simulate this circuit – Schematic created using CircuitLab

You can install capacitors INSIDE the footprint, on back side of the PCB. This may help.

  • \$\begingroup\$ yes,the 700Mhz peak it's always present without even plugging my board. I don't understand the meaning of Get some bypassing UNDER THE package,..." can you please clarify ? \$\endgroup\$
    – C.Hicham
    Commented Nov 22, 2018 at 16:48
  • \$\begingroup\$ With power OFF, that 700MHz peak exists? \$\endgroup\$ Commented Nov 22, 2018 at 19:56
  • \$\begingroup\$ Your bypass caps are 10mm away from the package. Get a 0102 SMT (1mm by 2mm) and solder that right at the epoxy of the IC. Then ask the manufacturer about soldering on back side of the PCB, to a VDD_via placed INSIDE the footprint. This will loop back the current flow, and reduce the loop area and thus reduce the inductance. \$\endgroup\$ Commented Nov 23, 2018 at 1:58

It really doesn't take much lead length at these frequencies to make a capacitor look like an inductor. I know it's inconvenient to have SM caps on both sides of the board but placing caps on the underside may help shorten traces. Vias nearer to pads. Multiple vias on ground pads. Another thing that sometimes occurs is that a large capacitor, beyond its self resonant frequency looks like an inductor and then resonates with a smaller cap in parallel to form a high impedance. Sometimes fewer caps is better.

  • \$\begingroup\$ Indeed, in term of pure distance, going through Vias will be shorter but it's not recommanded to use Vias before a decoupling capacitor as mentionned in their hardware design imgur.com/a/AukgJQE \$\endgroup\$
    – C.Hicham
    Commented Nov 22, 2018 at 16:58

As you are adding ferrites to isolate the power stage and its bypass capacitors from the rest of the PCB, It is not surprising at all. The LDO has no hope of doing anything useful at those frequencies.

At those frequencies a PCB would look like a forest of somewhat high-Q LC tanks in parallel. The amplifier stage is injecting multiple harmonics into this forest, and its power lines are reacting to the reflections of those injections, modulating its output and making it unstable.

Ferrites introduce some inductance, but much more importantly quite a bit of loss. This isolates the board, and all of its reflections, from the power stage. And now all of the harmonics only need to deal with the short traces to the capacitors.

Many designers place small resistors in series with supply pins, even at lower frequencies, to reduce PCB-IC interactions and improve emissions. Ferrites serve this role.


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