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I'm trying to design this circuit using gm/Id method.

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I am already able to achieve the desired GBWP and Gain (this is just a simple example so I'm just trying to achieve both) but I'm having trouble deciding on which length values I should use. I know that increasing the length increases the output resistance and in turn, the intrinsic gain. However, I'm not sure which other parameters I should consider when increasing the length. How should I choose which length I should use for NMOS? I also noticed that one can also use lengths where both the NMOS and PMOS have the same output resistance. When should I do this (making resistances equal)? And when should I not? What would happen if an NMOS's or PMOS's resistance is larger than the other?

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  • \$\begingroup\$ Draw your small-signal model. And discuss how the VDD is or is not affecting the possible gain. And consider what output VPP you need. Once you have a small-signal model, including VDD effects (the Vearly in bipolar, or Lambda in fets), you can better probe via equations the solution space. To bias this into linear regions (given the possible high gain), you'll need to provide DC feedback, just like Av = 100,000X opamps need DC feedback. \$\endgroup\$ – analogsystemsrf Nov 23 '18 at 15:17

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