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I'm trying to set LOC constraint while specified in verilog code (via verilog attribute). Previous research on the internet gave reasons to think that this sort of construction should work:

///////////////////////////////////////////////////////////////// code begins

module wrapper(in, out);

    input in;

    output out;

    (* BEL="A6LUT", LOC="SLICE_X4Y4") INVERT inverter_instance1(in, out);

endmodule


module INVERT(in, out);

    input in;

    output out;

    assign out = !in;

endmodule

///////////////////////////////////////////////////////////////// code ends

Yet when implemented, Vivado just ignores that attribute syntax and implements the LUT into slice X0Y1 by default. Any thoughts on what's going on here?

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  • \$\begingroup\$ I have not got the details at hand but what I remember is that you should start the comment with a specific word which indicates that a constraint is coming. Something like /* synthesis ... */ \$\endgroup\$
    – Oldfart
    Nov 23 '18 at 14:01
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You should begin with reading the Xilinx constraints guide.

I did that for you and found this as example code:

// synthesis attribute loc [of] {instance_name|signal_name} [is] location;

The document is not very clear as where exactly you should place that code but I remembered that it should be just before the closing semicolon. In which case you should use /* ... */

INVERT inverter_instance1(in, out) /*  Here */ ;

I tried it on the following code and the inverter moved from location X0Y5 (without constraints ) to X4Y4 (with constraints).

module invrt(input in, output out);
   INV inverter_instance1(out, in) /*  synthesis BEL="A6LUT", LOC="SLICE_X4Y4" ; */;
endmodule
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  • \$\begingroup\$ I'll take a closer look at Xilinx's guide, but I'm no getting it to work with that code neither (the LUT remains attached to X0Y1). Thx anyway \$\endgroup\$ Nov 23 '18 at 15:15

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