Vivado LOC constraint via Verilog code

Question

I'm trying to set LOC constraint while specified in verilog code (via verilog attribute). Previous research on the internet gave reasons to think that this sort of construction should work:

///////////////////////////////////////////////////////////////// code begins

module wrapper(in, out);

    input in;

    output out;

    (* BEL="A6LUT", LOC="SLICE_X4Y4") INVERT inverter_instance1(in, out);

endmodule


module INVERT(in, out);

    input in;

    output out;

    assign out = !in;

endmodule

///////////////////////////////////////////////////////////////// code ends

Yet when implemented, Vivado just ignores that attribute syntax and implements the LUT into slice X0Y1 by default. Any thoughts on what's going on here?

Answer 1

You should begin with reading the Xilinx constraints guide.

I did that for you and found this as example code:

// synthesis attribute loc [of] {instance_name|signal_name} [is] location;

The document is not very clear as where exactly you should place that code but I remembered that it should be just before the closing semicolon. In which case you should use /* ... */

INVERT inverter_instance1(in, out) /*  Here */ ;

I tried it on the following code and the inverter moved from location X0Y5 (without constraints ) to X4Y4 (with constraints).

module invrt(input in, output out);
   INV inverter_instance1(out, in) /*  synthesis BEL="A6LUT", LOC="SLICE_X4Y4" ; */;
endmodule