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In DDR3 memory there is a signal called DQS that I have several question about.

  1. What is DQS abbreviated for? specially Q
  2. What is the purpose of data strobe in DRAM and why not use simple clock.
  3. Is DQS on DRAM chip an output or an input coming from memory controller?
  4. What is relation of DQS to CLK, Address and control signals? In length matching of DDR signals, I found that flight time of "CLK+Address+Ctrl signals" are not related to flight time of Data Lane. how this is possible. Is it means that they are completely unrelated?

Explanation

Micron TN4605 explain the need for Data Strobe:

In a purely synchronous system, data output and capture are referenced to a common, free-running system clock. However, the maximum data rate for such a system is reached when the sum of output access time and flight time approaches the bit time (the reciprocal of the data rate). Although generating delayed clocks for early data launch and/or late data capture will allow for increased data rate, these techniques do not account for the fact that the data valid window (or data eye) moves relative to any fixed clock signal, due to changes in temperature, voltage, or loading. So, to allow for even higher data rates, data strobe signals were added to DDR devices.

But I don't understand the explanation for maximum data rate for purely synchronous system

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  1. The Q is just some ancient notation. Data signals are called DQ and data strobe is DQS

  2. Data strobe is the clock signal for the data lines. Each data byte has their own strobe

  3. It is bidirectional signal. It is transmitted by the same component as the data signals. By the memory controller on write and the by the memory on read commands.

  4. Control and address signals are unidirectional and clocked by the CLK signal. DQS runs the same speed as CLK but they are not synchronized.

Let's imagine time of flight for all signals is 1ns.

Situation with only one clk that is transmitted by the controller:

-During write there is no problem. Data signals can be clocked to the CLK signal and everything is fine. If traces are length matched you can use timing tolerances tighter than the time of flight.

-During read there is a problem. The controller must first transmit the clock to memory, where it arrives 1 ns later. Then the memory sends data bits to the controller and this takes another nanosecond. There is 2 ns skew, which limits how fast you can transmit.

When the same component that sends the data sends the clock, it is all synchronized. Data can be transmitted even faster than what is the time of flight

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    \$\begingroup\$ Thanks, you saved me couple of hours. Still I'm wondering why Q in DQS, but not F? which is not important at all :). Thank you again \$\endgroup\$ – pazel1374 Nov 23 '18 at 22:19
  • \$\begingroup\$ Q is used because of Q in FlipFlop, see electronics.stackexchange.com/questions/281813/… \$\endgroup\$ – pazel1374 Nov 23 '18 at 22:34
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The reason why you need a data strobe is because of clock skew. If a clock signal is high for 20 seconds, the amount of time it is high for both the sender and receiver at the same time is going to be less than 20 seconds. It does not overlap perfectly. The sender's 20 seconds starts earlier than the receivers 20 seconds. The smaller the duration of the signal or the further apart the sender and receiver, the smaller the shared window (overlap region) gets, until eventually the windows no longer overlap at all (because the skew becomes greater than length of time the signal is high for at the sender – the receiver's 20 seconds starts when the signal at the sender has gone low). Obviously the difference at this macroscopic time scale is unnoticeable. But at a nanosecond timescale, the receiver could send back the data and it arrive when the clock at the sender is back to low.

DDR4-4000 has a 0.4ns clock cycle. This means the signal is high for the memory controller for 0.2ns. Light travels 6cm in 0.2ns. If the DDR bus were 2cm long then by the time the high signal reaches the DIMM and for it to instantly assert data on the clock and return to the memory controller, it will already be 2/3 of the way through the time that the clock is high for. This means that the memory controller only has 1/3 of the usual time to latch the data. If the bus were 3cm long then the clock level it expects to latch the data on (after TCL (CAS latency) has elapsed) will latch all zeroes with no way of knowing whether the memory address contained 8 bytes of zeroes or whether it was a hardware issue.

This is how clock skew limits high clock speeds (the smaller the clock interval, the closer the components have to be, and the DIMM pins just cannot geometrically be less than 2cm away from the memory controller) or 'how fast you can transmit', which can be eliminated using the DQS pair.

The memory controller could always factor in clock skew and bus speed/distance into the timings, but this is dirty and requires extra logic. It makes sense to eliminate any strict reliance on TCL by allowing the DIMM rank to send the data + clock signal when it wants and the data will be automatically latched in at the accompanying clock. The memory controller operations are then not strictly bound by the DRAM timings – it can operate slower if it wants (not faster, obviously). It acts as a marker for the incoming data so the memory controller doesn't have to keep track of it.

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