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In DDR3 memory there is a signal called DQS that I have several question about.

  1. What is DQS abbreviated for? specially Q
  2. What is the purpose of data strobe in DRAM and why not use simple clock.
  3. Is DQS on DRAM chip an output or an input coming from memory controller?
  4. What is relation of DQS to CLK, Address and control signals? In length matching of DDR signals, I found that flight time of "CLK+Address+Ctrl signals" are not related to flight time of Data Lane. how this is possible. Is it means that they are completely unrelated?

Explanation

Micron TN4605 explain the need for Data Strobe:

In a purely synchronous system, data output and capture are referenced to a common, free-running system clock. However, the maximum data rate for such a system is reached when the sum of output access time and flight time approaches the bit time (the reciprocal of the data rate). Although generating delayed clocks for early data launch and/or late data capture will allow for increased data rate, these techniques do not account for the fact that the data valid window (or data eye) moves relative to any fixed clock signal, due to changes in temperature, voltage, or loading. So, to allow for even higher data rates, data strobe signals were added to DDR devices.

But I don't understand the explanation for maximum data rate for purely synchronous system

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  1. The Q is just some ancient notation. Data signals are called DQ and data strobe is DQS

  2. Data strobe is the clock signal for the data lines. Each data byte has their own strobe

  3. It is bidirectional signal. It is transmitted by the same component as the data signals. By the memory controller on write and the by the memory on read commands.

  4. Control and address signals are unidirectional and clocked by the CLK signal. DQS runs the same speed as CLK but they are not synchronized.

Let's imagine time of flight for all signals is 1ns.

Situation with only one clk that is transmitted by the controller:

-During write there is no problem. Data signals can be clocked to the CLK signal and everything is fine. If traces are length matched you can use timing tolerances tighter than the time of flight.

-During read there is a problem. The controller must first transmit the clock to memory, where it arrives 1 ns later. Then the memory sends data bits to the controller and this takes another nanosecond. There is 2 ns skew, which limits how fast you can transmit.

When the same component that sends the data sends the clock, it is all synchronized. Data can be transmitted even faster than what is the time of flight

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  • \$\begingroup\$ Thanks, you saved me couple of hours. Still I'm wondering why Q in DQS, but not F? which is not important at all :). Thank you again \$\endgroup\$ – pazel1374 Nov 23 '18 at 22:19
  • \$\begingroup\$ Q is used because of Q in FlipFlop, see electronics.stackexchange.com/questions/281813/… \$\endgroup\$ – pazel1374 Nov 23 '18 at 22:34

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