In DDR3 memory there is a signal called DQS that I have several question about.
- What is DQS abbreviated for? specially Q
- What is the purpose of data strobe in DRAM and why not use simple clock.
- Is DQS on DRAM chip an output or an input coming from memory controller?
- What is relation of DQS to CLK, Address and control signals? In length matching of DDR signals, I found that flight time of "CLK+Address+Ctrl signals" are not related to flight time of Data Lane. how this is possible. Is it means that they are completely unrelated?
Micron TN4605 explain the need for Data Strobe:
In a purely synchronous system, data output and capture are referenced to a common, free-running system clock. However, the maximum data rate for such a system is reached when the sum of output access time and flight time approaches the bit time (the reciprocal of the data rate). Although generating delayed clocks for early data launch and/or late data capture will allow for increased data rate, these techniques do not account for the fact that the data valid window (or data eye) moves relative to any fixed clock signal, due to changes in temperature, voltage, or loading. So, to allow for even higher data rates, data strobe signals were added to DDR devices.
But I don't understand the explanation for maximum data rate for purely synchronous system