# Cascading an Op Amp at a desired frequency question

So I have a lab practical with the instructions

"Demonstrate an operational amplifier circuit which may consist of one or two op amps with a gain of X (±10%) and a -3dB frequency exceeding Y kHz. The sign of gain can be + or -. "

I understand the operation and build of an amp and this is actually the second time doing this lab as I screwed it up the first time. The first time I was asked to design an amplifier with a gain of 80 with a frequency of around 1kHz. I used a circuit similar to the one depicted below to do this. Obviously my resistor values were different because I required a different gain.

As my understanding, depending on the sign of the gain dictates whether I used the noninverting (-R2/R1) or the inverting equation (1+R2/R1). Using these equations and the desired gain I can choose resistor values that give my desired gain. I also understand that if the desired gain is high enough I will have to cascade op amps. What I'm confused about is designing around the desired -3dB frequency. I guess I would like someone to explain where the -3dB frequency comes in to play in designing an op amp circuit.

• You do realize that the circuit shown has a gain of 20, not 80. And that a feedback resistor value of 460$\Omega$ is a bit low for most op-amps. Nov 24, 2018 at 18:06
• Yes I didn't use any of the values shown in that picture. I just used a similar model for my circuit. Nov 24, 2018 at 18:21

What I'm confused about is designing around the desired -3dB frequency

I think the question is trying to test you on your understanding of the open-loop gain for an op-amp and how the 3dB point changes as you lower the gain with feedback resistors. For instance: -

In the example above, the feedback and input resistors are chosen so that the "closed-loop" gain at DC is 20 dB (a real number gain value of 10). At this level of amplification you can see that the op-amp will run-out-of-steam at a frequency about 50 kHz. This is the approximate 3 dB point (half power point). If we chose a closed loop gain of 55 dB (G = 560), the 3 dB point would be much lower at 1 kHz.

As an aside, this introduces the concept of the op-amp having a numerically fixed (well, fairly fixed) value of gain x bandwidth often called the GBWP or gain-bandwidth-product. G = 10 and BW = 50 kHz is pretty close to G = 560 and a BW of 1 kHz. I'm sure with a better picture of the open-loop gain it would be numerically quite close in both scenarios.

So, with two cascaded op-amps, the best (highest) 3 dB point you can get is when both have the same gain because, if one had a much smaller gain than the other, the device operating at the higher gain would dictate the 3 dB point and this will inevitably be lower than if both gains (and both op-amps) are the same.

• So what is exactly the correlation between the resistor values and the 3dB point? Fundamentally everything you said makes perfect sense but I'm am still a bit confused about choosing the correct resistor values with a specific 3dB point in mind. Nov 24, 2018 at 18:02
• That graph is different for each model of op-amp so the 3 dB point only correlates to resistor values when you know the specific op-amp. Read about gain-bandwidth product. Nov 24, 2018 at 18:05
• Once you're using high enough resistor values there's not much correlation between resistor value and the 3dB point. The correlation is between the circuit's DC gain and the 3dB point. Nov 24, 2018 at 18:05
• The only way to "see" the effects is to calculate and observe. Design a stage with X gain, and observe the frequency rolloff. Design another with Y gain and observe. Now mulitply the two and see what you get. Do this for other combinations of gain. Stop guessing asking for other people to explain things. Nov 24, 2018 at 18:20
• Warning ----- the total of capacitances on the Vin- pin (the virtual ground) may set the bandwidth. And expect phase-shifts to cause extending settling or ringing or oscillation. Photodiode circuits often have this problem; the cure is a 1pF or 5pF or 20pF feedback capacitor. Nov 24, 2018 at 19:04