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I'm currently making a PCB with 2 ethernet ports and a CPU running at 200+ Mhz. This isn't the fastest PCB by any means and I don't foresee any issues with the placements, however in the future I might want to know how to do this properly.

And before anyone asks, yes I did in fact check the hundreds of other posts for this subject. The problem is that it's conflicting each other every other post. One person says the loop matters, the next says don't do vias, the next says power should hit cap first then chip etc.... It's confusing as hell.

This is kind of the style I'm using for this particular board:

enter image description here

It's a 4 layer PCB with signal-ground-power-signal layers. I simply route the vias to these massive planes in the picture(sidenote: is it ok to occasionally route other voltages over the power plane?). I'm also thinking of moving the vias on the inside of the chip directly on top of the SMD pads but I'm not sure if the manufacturer(Eurocircuits in this case) allows this.

What is the correct way of placing decoupling capacitors?

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  • \$\begingroup\$ Recently, a question rose about a misbehaving Transmitter at 6,000 MHz. The PCB had 1cm of PCB trace between the IC and the bypass caps. As you have already done, place the bypass caps right against the VDD pins. \$\endgroup\$ – analogsystemsrf Nov 24 '18 at 18:51
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    \$\begingroup\$ Your vias on the caps are nice from electrical perspective but the horror from soldering perspective. Don't place them under the cap. They aren't a flat surface. \$\endgroup\$ – Janka Nov 24 '18 at 18:59
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What is the correct way of placing decoupling capacitors?

Rule 1 - as close to the chip's pins as physically possible.

Rule 2 - Keep ground plane vias from the decoupling cap pins as close as possible and, if necessary on heavy duty current pins, use several vias.

I'm not too worried that the power feeds the "other" end of the pin providing rule 1/2 is observed and there is nothing in the chip's data sheet that says otherwise. Sometimes it's physically impossible to have power plane vias on the outside of the chip's pin.

Rule 3 - do what the data sheet suggests (or better)

Rule 4 - use the most appropriate type of capacitor and take note of the self-resonant frequency of some capacitor types (making them inappropriate).

is it ok to occasionally route other voltages over the power plane?

Sure but try not to do this too much on the ground plane.

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  • \$\begingroup\$ @ Andy Is the OP asking about slitting the ground plane, with the "route other voltages over the power plane" ? \$\endgroup\$ – analogsystemsrf Nov 24 '18 at 18:59
  • \$\begingroup\$ @analogsystemsrf I don’t read that in the question so maybe the op can clear this up? \$\endgroup\$ – Andy aka Nov 24 '18 at 19:05
  • \$\begingroup\$ The thing about the power plane trace was just something i thought of randomly. I meant routing the 1.2V over the power plane which in my case is 3.3V. They're not long traces but it keeps the design simple. \$\endgroup\$ – Tryphon Nov 24 '18 at 19:27
  • \$\begingroup\$ Routing a stub from the 1.2V plane either on the 3.3V plane (i.e., a cutout in the 3.3V plane) or over the 3.3V plane should be fine as long as they share a common ground, unless there's a signal trace that may have a lot of high-frequency content that cuts across that 1.2V trace. \$\endgroup\$ – TimWescott Nov 24 '18 at 20:55

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