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I am designing some boards that are powered and communicate through Cat 5 cables using a bit banged form of protocol inspired by quad spi.

Using the bus network topology in a half duplex manner, I am able to communicate reliably with 10kHz clock.

Since I am using the classic atmega328p-au do I have to worry about putting an external clock or it should do the job fine with just the internal RC circuit?

Modified image of this:

enter image description here

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  • \$\begingroup\$ could be interesting WRT crosstalk \$\endgroup\$ – Jasen Nov 24 '18 at 19:31
  • \$\begingroup\$ @Jasen are you thinking of whitened clocks? \$\endgroup\$ – Marcus Müller Nov 24 '18 at 19:32
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    \$\begingroup\$ cat5 has 4 pairs, this schme has 6 signals - it's going to get messy however it's done. I've also seen dielectric absorbtion on cat5 which may mess with the slow signals, and with the data if there are long runs of 1s or 0s. \$\endgroup\$ – Jasen Nov 24 '18 at 19:38
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    \$\begingroup\$ That was kind of hard to read. I've split it into sentences and paragraphs as seemed reasonable to me. Let me know if I got it wrong. \$\endgroup\$ – JRE Nov 24 '18 at 19:56
  • \$\begingroup\$ @Jasen the other two are GND and 12V to power the boards and each board consumes 50mA. \$\endgroup\$ – Lucas Alexandre Nov 24 '18 at 20:40
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SPI is a self clocked protocol, so having clock speeds match at both ends of the wire is not important, the internal oscillator should be fine.

maintaining signal integrity over cat 5 used in such an off-label way could be challenging, I hope all your cables are short.

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You don't need a reliable clock at all, since this is a synchronously clocked bus:

Your CLOCK signal determines when bits are sampled / set, so all that must be the case is that the data bits are latched on the edge of your clock signal.

So, no, there's no need for external clocking.

In fact, in SPI, a clock cycle can take anything from 1/max freq to an eon (as long as both ends of the link stay intact and powered for that eon).

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