For two input AND gate what will be the output if one input is 3.3v and other input is 5v? Ref: VCC=5v, GND=0v.

  • 2
    \$\begingroup\$ What does the datasheet say? \$\endgroup\$
    – Hearth
    Nov 25, 2018 at 1:34
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    \$\begingroup\$ What are your thoughts? What do you think might affect the output? \$\endgroup\$
    – The Photon
    Nov 25, 2018 at 1:37
  • \$\begingroup\$ Also, what logic standard? CMOS or TTL will give the same result for this particular question, but there are others out there: ECL, CML, ... \$\endgroup\$
    – The Photon
    Nov 25, 2018 at 1:38
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    \$\begingroup\$ This is completely unanswerable without more information. Provide the specifications for the specific AND gate you have in mind. \$\endgroup\$ Nov 25, 2018 at 2:29

1 Answer 1


It depends entirely on what logic family the gate comes from.

If it's a TTL gate, the output will be high, because any input above about 0.8 V is considered high.

If it's an HC family CMOS gate, in principle there's no guarantee what the output will be. To be a valid high input, the voltage must be at least \$0.7 \times V_{dd}\$. Realistically, 3.3 V will always be effectively high, and the output will be high, but specifications like propagation delays will not be guaranteed.

If it's an ECL gate, 3.3 V is too low to be a valid logic high and the output will be low (low being a voltage between \$V_{cc}-1.95\$ and \$V_{cc}-1.63\$ for the MECL 10H family).

Of course there are many other logic families, so you should be sure you know which one you are using when trying to answer this kind of question.


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