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The internal clock (Q1–Q4) of PIC Micro controller runs at a quarter of the oscillator frequency (FOSC/4).

My question is if i divide the frequency with 4 Then the timer period of each clock pulse will increase 4 times.

enter image description here

However this picture is confusing. it shows after the internal circuitry divides the clock into four even quadrature clocks. the timer period of each clock (i.e Q1, Q2, Q3, and Q4) less than the main primary oscillator(that is connected to the OSC1 and OSC2 pins). But i think time period of each clock pulse must be 4 times time period of main primary oscillator. enter image description here

  1. Can anybody explain the above??

2.What is oscillator cycle?? the frequency of oscillator cycle??

  1. What is machine cycle ??
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  • \$\begingroup\$ FYI the upper diagram which you copied into your question, shows a divide-by-2, not a divide-by-4. \$\endgroup\$ – SamGibson Nov 26 '18 at 18:36
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The oscillator frequency is divided by four, so a machine cycle takes some integer number of 4 oscillator cycles. The oscillator cycle is just the reciprocal of the oscillator frequency, so if the oscillator is 16MHz, each oscillator cycle is 62.5ns.

In the case of the mid-range PIC, that number is 1 or 2, so that will be 4 or 8 oscillator cycles. In other words, if the oscillator is 16MHz, each instruction will take 250ns or 500ns.

The Q1-Q4 states are important when you want to exactly when (against what oscillator edge) the outputs appear at the pins, and when the inputs are sampled, and for similar reasons. Usually you don't need to worry about the Q states and can simply consider the processor running at fosc/4.

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