According to answers to this previous question, routing traces between the pads of SMD caps/resistors, as shown in the picture, is not dangerous as long as trace to pad clearances are obeyed and the possibility of crosstalk is accounted for.
That being said, this type of answer sounds incomplete to me: while the clearance between trace and pads may be ok, the via under the SMT component and bottom of the SMT component are separated only by a thin layer of solder mask, and it seems unsafe to rely on that kind of insulation. This source seems to agree (about solder mask being bad at insulating, not about the trace between pads question), and IPC-2221 also states something to that effect: "Complete reliance on coatings to maintain high surface resistance between conductors shall be avoided."
So, shouldn't one also consider the possibility of this insulation failing? Wouldn't that make this kind of design choice bad? Could I estimate how much voltage a SMT component can handle between its bottom and a trace underneath it?