# Is there anything macro-like, in VHDL?

I have a little piece of code, that applies again and again, in different places. The places are too irregular, the code is too small, and the input and varies too much to be able to use an entity.

Is there anything macro like in VHDL?

for example:

macro do_something(input_a, output_b);
counter_1 <= counter_1 + 1;
output_b <= input_a & other_input;
other_output <= input_a;
end macro;
-- note: since this uses other_output, it can obviously only be used in one process!

process(clock) begin
if some_condition then
do_something(local_signal_p,local_signal_q);
elsif some_other_condition then
do_something(local_r,local_s);
end if;
end process


The idea would be that the "do_something" would be replaced by the individual instructions.

Is there such a thing?

I would advice to use a procedure over a function for this, since putting this in a function results in impure functions, which always bring along a number of issues. Procedures are exactly what you describe here. Syntax for your example:

procedure proc_do_something(input_a : in integer range 0 to c_argument_max,
output_b : out integer range 0 to c_argument_max) is
begin
counter <= counter + 1;
output_b <= input_a & other_input;
other_output <= input_a;
end procedure proc_do_something


Definition is done between the is and begin of the process you want to use it in. I know declaration can theoretically be done in packages in case of blackbox behaviour, although I've never seen that done before.

• IEEE Std 1076-2008 10.5.2.2 Executing a simple assignment statement "If a given procedure is declared by a declarative item that is not contained within a process statement, and if a simple waveform assignment statement appears in that procedure, then the target of the simple waveform assignment shall be a formal parameter of the given procedure or of a parent of that procedure, or an aggregate of such formal parameters. ...". This allows drivers to be determined statically. – user8352 Nov 29 '18 at 0:56

I think functions would do what you're looking for

function BOOL_TO_SL(X : boolean)
return std_ulogic is
begin
if X then
return '1';
else
return '0';
end if;
end BOOL_TO_SL;

• functions are great for intermediate calculations (as in your answer), but horrible if you want to change the state of the entity they're used in (as in the question). Impure functions have always lead to synthesis issues in each project I've seen them used in. – DonFusili Nov 26 '18 at 9:28