Sample time of PI controller

Question

I have designed a closed loop current control (PI controller) of a DC-DC converter in continuous time domain and it is working fine. The next task is discreetization of the controller and implement it in FPGA Spartan 6. FSW is 40 kHz and I am sensing inductor current with an LEM sensor and then a low pass filter of 400 Hz and then into my ADC in designed hardware.

Now the question is while discreetization of controller, what sample time do I use? In VHDL code I have written, I calculate PI output at every rising edge of clk (50 Mhz). This would mean a TS of 20 ns. Could there be any issue with sampling so fast? My understanding is that I should sample at least a decade faster than the controller bandwidth, which I have designed to be at least a decade lower than my switching frequency.

Any advice is much appreciated.

Answer 1

I believe you are conflating two rules of thumb

1. separation in loop bandwidths when dealing with nested loops
2. Sampling of data

Loop bandwidth

There is a general rule of thumb that inner control loops should have a bandwidth around 10x that of the outloop. The reason for this is so the reactions of the inner loop should not result in any major changes in the outer loop.

Position (10Hz) -> Velocity ( 100Hz) -> Current (1kHz) -> Voltage (10kHz)

Why 10x ? consider a 1st order system,

\$ mag = \frac{1}{\sqrt{ \frac{f}{f_c}^2 + 1 }}\$

\$ angle = atan(\frac{f}{f_c}) \$

If the demand was capable of changing at the bandwidth of the loop there would be 70% reduction in magnitude and a 45deg phase shift.

By ensuring the inner loop is 10x that of the outer, the inner loop should be able to track demand changes to within 99.5% of its amplitude and 5degree while ensure any change in feedback is at the loops bandwidth.

As with all rules of thumb, take with a pinch of salt... Sometimes more separation is required, sometimes due to other constrains a smaller separation has to be tolerated. However, a rule of thumb is a good place to start.

Imagine if that separation was to shrink... the inner loops ability to react to demand changes starts becoming extremely restrictive to the point of instability: The additional phase shift in the forward path with regards to the resultant feedback producing a phase shift that can produce a feed-forward loop.

Digital PI

The implementation of a digital PI is essentially a gain, and accumulator and a summation. However, it is a bit more than that. There is typically three types of digital integrators

1. Forward Euler \$y_n = y_{n-1} + K_i \Delta t \cdot x_{n-1}\$
2. Backwards Euler \$y_n = y_{n-1} + K_i \Delta t \cdot x_{n}\$
3. Trapizoidal \$y_n = y_{n-1} + K_i \Delta t \cdot (x_n -x_{n-1})/2\$

\$K_i \Delta T\$ is typically just reduced to the integral time constant to simplify implimentation

The forward Euler is extremely unstable, especially with large integral timesteps. Backwards Euler is the workhorse of digital integrators and Trapizoidal is reserved for those wanting the additional accuracy.

From your working example you have stated three key pieces of infomation

1. Fsw = 40kHz -> The current loop could operate at 4kHz
2. Fclk = 50MHz
3. ADC sampling rate ????
4. Anti-Aliasing filter at 400Hz

Your present implementation has the PI operating at system clock rate. There is two issues with this but it isn't to do with whether the PI can operate as a PI

As previously mentioned, the gain of a digital integrator is proportional to the integration time-step \$\Delta T\$. If you want a relatively large integral time-constant with a low time-step, you will need a very large \$K_i\$ to realise a specific integral gain. A multiplication block that can accept a high value but also realise a specific resolution will be physically quite large. You may choose to just operate this as an accumulator but then your effective s-domain gain is that of your system clock.

The second problem is the harsh constrains you are imposing on the synthesis. In one system clock period you are expecting the synthesis tool to complete

1. Difference
2. Proportional multiplication
3. Backwards Euler (multiplication + addition)
4. Anti-windup checks
5. Final summation

This is quite a demand, especially when it really isn't needed. You have not stated the ADC sampling rate, but you have stated the analogue anti-aliasing filter.

With an anti-aliasing filter at 400Hz, you cannot be interested in any component above 4kHz ( 1% amplitude, 84degree phaseshift). If this is the case, why update the PI loop every 20ns when it is being present with new relevant information every 250us?

There is a massive disparity between your forward path and your feedback and this is fundamentally where the problem is. Your feedback should be acquired again at least 100x that of the loop in question. Why? the proportional term is extremely susceptible to feedback delays. If the bandwidth of the loop in question has a bandwidth which equals that of the forward path, the loop response will exhibit +5dB at the natural frequency, something you do not want

You have selected 40kHz switching frequency for some reason, hopefully due to a current ripple requirement with respect to the forcing voltage. I am going to assume the reason you have a 400Hz analogue LPF on the current feedback is to completely suppress the switching component.

My recommendation is

1. Confirm the needed switching frequency.
2. Tune your current loop to be a 10th of this.
3. Have the ADC's clocked at least 10x the switching frequency.
4. Strobe your PI loop at the ADC rate
5. Constraints on implementation such that the PI calculations are completed within the ADC sample window
6. IF the switching component is causing a problem, implement a biquad filter and tune it as a band-stop. This should roll off the 40kHz component a lot steeper than your 1st order analogue