I have designed a closed loop current control (PI controller) of a DC-DC converter in continuous time domain and it is working fine. The next task is discreetization of the controller and implement it in FPGA Spartan 6. FSW is 40 kHz and I am sensing inductor current with an LEM sensor and then a low pass filter of 400 Hz and then into my ADC in designed hardware.

Now the question is while discreetization of controller, what sample time do I use? In VHDL code I have written, I calculate PI output at every rising edge of clk (50 Mhz). This would mean a TS of 20 ns. Could there be any issue with sampling so fast? My understanding is that I should sample at least a decade faster than the controller bandwidth, which I have designed to be at least a decade lower than my switching frequency.

Any advice is much appreciated.

  • \$\begingroup\$ From where did you get that you should sample at a decade lower than your controller bandwidth? Are you getting that backwards? \$\endgroup\$ Nov 26, 2018 at 22:05
  • \$\begingroup\$ If your sampling is slower than the phenomena you are trying to control, you're going to have a bad time. It's like driving but only looking up from your phone every minute. \$\endgroup\$
    – EasyOhm
    Nov 26, 2018 at 22:32

1 Answer 1


I believe you are conflating two rules of thumb

  1. separation in loop bandwidths when dealing with nested loops
  2. Sampling of data

Loop bandwidth

There is a general rule of thumb that inner control loops should have a bandwidth around 10x that of the outloop. The reason for this is so the reactions of the inner loop should not result in any major changes in the outer loop.

Position (10Hz) -> Velocity ( 100Hz) -> Current (1kHz) -> Voltage (10kHz)

Why 10x ? consider a 1st order system,

\$ mag = \frac{1}{\sqrt{ \frac{f}{f_c}^2 + 1 }}\$

\$ angle = atan(\frac{f}{f_c}) \$

If the demand was capable of changing at the bandwidth of the loop there would be 70% reduction in magnitude and a 45deg phase shift.

By ensuring the inner loop is 10x that of the outer, the inner loop should be able to track demand changes to within 99.5% of its amplitude and 5degree while ensure any change in feedback is at the loops bandwidth.

As with all rules of thumb, take with a pinch of salt... Sometimes more separation is required, sometimes due to other constrains a smaller separation has to be tolerated. However, a rule of thumb is a good place to start.

Imagine if that separation was to shrink... the inner loops ability to react to demand changes starts becoming extremely restrictive to the point of instability: The additional phase shift in the forward path with regards to the resultant feedback producing a phase shift that can produce a feed-forward loop.

Digital PI

The implementation of a digital PI is essentially a gain, and accumulator and a summation. However, it is a bit more than that. There is typically three types of digital integrators

  1. Forward Euler \$y_n = y_{n-1} + K_i \Delta t \cdot x_{n-1}\$
  2. Backwards Euler \$y_n = y_{n-1} + K_i \Delta t \cdot x_{n}\$
  3. Trapizoidal \$y_n = y_{n-1} + K_i \Delta t \cdot (x_n -x_{n-1})/2\$

\$K_i \Delta T\$ is typically just reduced to the integral time constant to simplify implimentation

The forward Euler is extremely unstable, especially with large integral timesteps. Backwards Euler is the workhorse of digital integrators and Trapizoidal is reserved for those wanting the additional accuracy.

From your working example you have stated three key pieces of infomation

  1. Fsw = 40kHz -> The current loop could operate at 4kHz
  2. Fclk = 50MHz
  3. ADC sampling rate ????
  4. Anti-Aliasing filter at 400Hz

Your present implementation has the PI operating at system clock rate. There is two issues with this but it isn't to do with whether the PI can operate as a PI

As previously mentioned, the gain of a digital integrator is proportional to the integration time-step \$\Delta T\$. If you want a relatively large integral time-constant with a low time-step, you will need a very large \$K_i\$ to realise a specific integral gain. A multiplication block that can accept a high value but also realise a specific resolution will be physically quite large. You may choose to just operate this as an accumulator but then your effective s-domain gain is that of your system clock.

The second problem is the harsh constrains you are imposing on the synthesis. In one system clock period you are expecting the synthesis tool to complete

  1. Difference
  2. Proportional multiplication
  3. Backwards Euler (multiplication + addition)
  4. Anti-windup checks
  5. Final summation

This is quite a demand, especially when it really isn't needed. You have not stated the ADC sampling rate, but you have stated the analogue anti-aliasing filter.

With an anti-aliasing filter at 400Hz, you cannot be interested in any component above 4kHz ( 1% amplitude, 84degree phaseshift). If this is the case, why update the PI loop every 20ns when it is being present with new relevant information every 250us?

There is a massive disparity between your forward path and your feedback and this is fundamentally where the problem is. Your feedback should be acquired again at least 100x that of the loop in question. Why? the proportional term is extremely susceptible to feedback delays. If the bandwidth of the loop in question has a bandwidth which equals that of the forward path, the loop response will exhibit +5dB at the natural frequency, something you do not want

You have selected 40kHz switching frequency for some reason, hopefully due to a current ripple requirement with respect to the forcing voltage. I am going to assume the reason you have a 400Hz analogue LPF on the current feedback is to completely suppress the switching component.

My recommendation is

  1. Confirm the needed switching frequency.
  2. Tune your current loop to be a 10th of this.
  3. Have the ADC's clocked at least 10x the switching frequency.
  4. Strobe your PI loop at the ADC rate
  5. Constraints on implementation such that the PI calculations are completed within the ADC sample window
  6. IF the switching component is causing a problem, implement a biquad filter and tune it as a band-stop. This should roll off the 40kHz component a lot steeper than your 1st order analogue
  • \$\begingroup\$ Thanks for such a descriptive answer. Lot of things are much clearer now. 1. Switching frequency is flexible for my application between 20-40kHz 2. I have taken care of my control loop BW, tuning them to have a BW a decade lower than 20 khz. 3. I am using an evaluation board which has an onboard ADC( MCP3204) , supply is 3.3 V, and max specified sampling rate is 100ksps at 5V supply and 50ksps at 2.7V supply, so for 3.3V I would guess max sampling rate and 60ksps. 4. Ok, so PI regulation clk in VHDL will be as per ADC sampling clk, right? 5. Can you please elaborate a bit on your point no. 5 \$\endgroup\$
    – Autobot
    Nov 27, 2018 at 13:40
  • \$\begingroup\$ Also, correct me if I am wrong. The thumb of rule to have sampling frequency atleast twice of signal frequency, won't really matter in my case, since that rule is to be able to reproduce signal with certain precision. Although, in my case I am just sampling filtered current signal, almost a dc value. So it's not like for an inductor current waveform of 40kHz, I need an ADC to have atleast 80ksps \$\endgroup\$
    – Autobot
    Nov 27, 2018 at 13:43
  • \$\begingroup\$ #5. you should be able to put timing constrains with regards to processes. Since the PI only really needs to update at twice the ADC rate (to the rev euler), by stating this in the timing constrains it offers you the option to implement sequential multipliers (smaller but slower). one of the beauties of FPGA's is being able to trade such things off to squeeze more out of the fabric \$\endgroup\$
    – user16222
    Nov 27, 2018 at 23:52
  • \$\begingroup\$ the "rule of thumb" of "at least twice" isn't a rule of thumb and it certainly isn't "at least". Nyquist theorem is a theorem. The rule of thumb would be to sample at 10x the frequency of interest to reconstruct the signal with enough information. Just because you have an almost DC value, the point of a closed-loop controller is to keep it DC, thus it must be able to react and cancel any AC components (typically due to load changes). Part of your system modelling should have considered the needs of your system to influence what it should do \$\endgroup\$
    – user16222
    Nov 27, 2018 at 23:55

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.