I have an ADC module. The board contains sensitive (10-100MHz) analogue parts and a high speed serial link (Aurora). The link uses scrambling algorithm, and I can choose the bit-rate. (I have much less data than the theoretical maximum of the link.)

My goal is to reduce the digital link disturbance on the sensitive analogue part.

We know the spectrum of a (scrambled) digital link. The ideal spectrum of a digital link.

(In a real application the fpattern is ~0Hz.)

The total power of a DC balanced square function is constant and independent on the bit-rate. So I hope that the power on the lower frequencies will reduce if I increase the bit-rate, because the full spectrum will be "more broadband" Am I right?

I cannot find mistake in my theory, however it is hard to imagine that higher frequencies makes less noise.

If I am right, should I choose the bit-rate of the link as fast as possible? (To reduce the disturbance of the analogue part)

  • 1
    \$\begingroup\$ You have not the model of coupling between analog and digital part. Base on the model, some coupling might be increased with frequency \$\endgroup\$
    – M KS
    Nov 27, 2018 at 9:42
  • \$\begingroup\$ I'm setting up the Signal Chain Explorer; next I'll insert the Electric and the Magnetic interferers, where edge-speed does matter. \$\endgroup\$ Nov 27, 2018 at 10:44
  • \$\begingroup\$ How close is the digital-serial-link to the "Sensitive analog circuit" ? \$\endgroup\$ Nov 27, 2018 at 18:18

1 Answer 1


Signals happen in time, not in frequency.

The "frequency" merely describes the periodicity of the peak correlation.

The interference, the trace-to-trace Electric Field Interference, the wire-to-loop Magnetic Field Interference, the edge-by-edge trashing of amplifiers by poor Power Supply Rejection, are not frequency-events. The trashing, the degradation of signals by the digital-data-movement, the diminished SNR, all happen in time.

However, if you do use a slow-scan spectrum analyzer, with 10KHz or 100KHz resolution bandwidth (equivalent to the older analog analyzers' IF Bandwidth), you will see the sin(x)/x or similar spectral plots as theory predicts. WHY?

Because the "narrow band resolution bandwidth" is equivalent to a long-duration correlation.

Yet your ADC is not a narrow-band correlation; and your signal-chain with 10MHz or 100MHz bandwidth are not narrow-band (10KHz or 100KHz) correlators.

In general, spectral manipulations such as you describe and as you question, are done to fool the FCC's testing methods.

These spectral manipulations REDUCE the density of the interference, on a per-Hertz basis. These spectral manipulations do not reduce the broadband interference, because signals Happen in time.

What should you do?

(1) Slow the edges of the bits in the digital link; this reduces the SlewRate, which reduces all forms of interference [ e.g. electric field coupling, magnetic coupling, ground upsets, VDD ringing]. You can slow the edges, without drawing high-speed currents, by using a differential RCR filter: 2 Rs in the 2 series Transmitter traces, that drive a differential Capacitor. 100 ohms and 100pF yield a 10,000 picosecond edge timeconstant; this will change the dataeye and cause delays, and may upset the Receiver.

(2) Ensure the ICs driving the digital link are very well bypassed at the driver IC VDD pins. Insert 10 ohm, or 1 ohm resistors in those VDD pins, or insert Ferrite Beads, to create local batteries, to ensure the high speed current surges drawn from the VDD rail is only supplied locally, and not from the more-global VDD PCB traces that will couple Electrically or Magnetically into your SignalChain.

You have a signal-fidelity challenge. Here is Signal Chain Explorer used to examine a similar signal-fidelity issue.

I've set up the tool for 60 nanovolt quanta out of the sensor and 1 milliVolt PP out of the sensor, with 1,000X gain; the chain of amplifiers/filters drives a 14-bit ADC with 1volt peakpeak input range.

To support the 100MHz bandwidth, I've used OpAmps with 1GHz UGBW, the 2nd and 3rd gain-stages are all 50 ohms Rin and 500 ohms Rfeedback. The LNA (stage#1) has 0.25 nanoVolt/rtHz noise density, with 50 ohm Rfeedback and 5.5 ohms to ground. Not knowing your bandwidth, I did not insert any PI matching.

The interference (the 4 Gargoyles) are: (HFI) 0.01 amps with 500 picosecond edges and (EFI) 0.1 volts with 500 picosecond edges, plus (PSI) 100MHz ringing on VDD. I did not enable the GPI (ground trash).

This first illustration is without the interferers. This shows the 60dB gain, the 3 gain stages (the first with about 7 ohms total Rnoise) and the final LowPassFilter to provide the ADC's sampling charge surges, the SNR at 50MHz (top right number: 29 dB) at FOI Frequency Of Interest, and the various thermal noise contributors.

Note the middle text summary: the Gargoyles are OFF, shown in the topright unchecked Gargoyle button. I'll set them up, and show the degraded SNR, in the next illustration. The mechanical structures between stages are how the interferer energy is injected: Efield by parallel-plate capacitor model, Hfield by wire-loop flux model, Power Supply trash by filter-models of the VDDbypassing with inductances and dampening plus finite PSRR, and finally some Ground spikes.

enter image description here

This next illustration (screen shot) shows the much worse SNR (-17dB) with the top-right Gargoyles ON (HFI/EFI/PSI), dominated by magnetic coupling into the signal chain. Each interstage path: sensor-LNA, LNA-stage2, stage2-stage3, etc , has 1 cm of PCB trace, 1mm wide and 0.06" (1.5mm) above the GROUND. This forms a loop to respond to magnetic fields, and offers a flat trace to be vulnerable to electric fields. Additionally, Power Supply trash at 100MHz ringing, is injected into the gain stages; PSRR at 100MHz is about zero dB.

enter image description here

And here is the Aggressor Summary, part of Analysis Details(button on right side). This shows enormous problem (-17dB SNR) from locating your data-link just 10mm (1cm) from the first signal-path (1mvpp Sensor into the LNA)

enter image description here

Notice the magnetic coupling into the very last trace of the signal-chain (Stage 5), between the LPF and the ADC, shows a 6 milliVoltRMS or 20mVPP interference.

This last stage interferer indicates the datalink may be degrading the ADC's performance. How close is the datalink routed to the ADC analog Vin? Or to the ADC's VDD bypass caps (which form a loop, remember, with Ground).


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