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I am using an FGMOSFET with tunneling gate and control gate as an analog memory for simulation in SPICE. I use -25V to inject electrons into the floating gate and 25V to remove electrons. Everything was going well until I read this paper:http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.27.7816&rep=rep1&type=pdf

and it says

Bidirectional tunneling can be used to add or remove electrons from a floating gate. This solution, however, requires either dual polarity high voltages, or a single polarity high voltage and a means for pulling the floating gate to this voltage when adding electrons, and pulling it near ground when removing them. Both approaches are unattractive. The dual polarity solution has a negative voltage much lower than the substrate potential; the single polarity solution does not support simultaneous memory reading and writing.

With the current technology we have, is this still valid. Are there technologies that allow a higher negative voltage than the substrate. I would really appreciate any help to point me in the right direction. Thanks

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  • \$\begingroup\$ You could always tie the N-WELL to GND and then use a MOSCAP to pull negative. You only need 10V to tunnel on 350nm. \$\endgroup\$ – b degnan Dec 13 '18 at 18:48
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The basic answer is yes. This is an intrinsic problem of IC design, your substrate has to be biased in a way that reverse-biases all parasitic PN junctions in the circuit. For most processes you have a P-substrate which means that the substrate has to be at the lowest potential in the circuit (generally -Vss). For a flash memory, where you also want a high density of elements, this limitation remains.

However:

  • In modern processes, where oxide thickness is just a few atoms, you can get tunneling going with less than 6V across a gate.
  • There are processes (e.g., trench-isolated) in which you can have isolated islands of substrate that can tolerate voltages in some cases in excess of ±300V.
  • High-voltage options on some processes can tolerate N-wells and P-wells at voltages in excess of 30V above the substrate.

With those considerations, you could segment your flash memory into trench-isolated sections, and drive those sections to a high enough voltage to tolerate positive and negative excursions.

But in most cases you might be better off by using injection processes (high-energy electron scattering at a junction edge) to place the electrons in the floating gate, not just a potential difference to drive them through tunneling.

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  • \$\begingroup\$ Thanks for the reply. Can you recommend any books, or articles about this topics. i have also read about triple well technology. Can I use that to isolate a substrate for the FGMOSFET. I'm using an nchannel fgmosfet \$\endgroup\$ – ElecNoob Nov 28 '18 at 5:26
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    \$\begingroup\$ @ElecNoob most of what I know about these technologies comes directly from fab datasheets. For an example, look at the XU035 CMOS deep N-well technology from XFAB (xfab.com/technology). Or at their SOI technologies. XU035 does have three well types. Yes, the deep N-well can be driven to a high voltage, while the enclosed P-well can go negative. \$\endgroup\$ – Edgar Brown Nov 28 '18 at 5:45
  • \$\begingroup\$ Thanks for the awesome replies and the link. I really appreciate it. :))) \$\endgroup\$ – ElecNoob Nov 28 '18 at 6:25

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