In Cliff Cumming's excellent paper on asynchronous vs synchronous resets, the following paragraph about the risk of metastability appears on page 19:

Attention must be paid to the release of the reset so as to prevent the chip from going into a metastable unknown state when reset is released. When a synchronous reset is being used, then both the leading and trailing edges of the reset must be away from the active edge of the clock.

The paper in particular notes that metastability is not a risk when asserting reset on a flip-flop with asynchronous reset, and explains why on page 23:

There is no reset metastability issue when reset is asserted because the reset signal bypasses the clock signal in a flip-flop circuit to cleanly force the output low

How can a asynchronous reset in a flip-flop be implemented such that asserting the reset carries no risk of metastability on the output?

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    \$\begingroup\$ Actually, I suspect that if you give a short enough reset pulse to an asynchronous reset, you could have metastability issues. \$\endgroup\$ – TimWescott Nov 29 '18 at 5:46

Asynchronous reset is level-sensitive so the timing relative to the clock edge is of no importance.

Think of the output cross-coupled gates of a master-slave flip-flop and add inputs to the gates to force the outputs to a given state. For example (from this website):

enter image description here

So long as the /RESET input is low, the /Q output must be high. In reality it has to be a bit more complex than this because you don't want glitching on the Q output. Here is the gate-level representation of a real D-FF (74LS74):

enter image description here

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