In Cliff Cumming's excellent paper on asynchronous vs synchronous resets, the following paragraph about the risk of metastability appears on page 19:
Attention must be paid to the release of the reset so as to prevent the chip from going into a metastable unknown state when reset is released. When a synchronous reset is being used, then both the leading and trailing edges of the reset must be away from the active edge of the clock.
The paper in particular notes that metastability is not a risk when asserting reset on a flip-flop with asynchronous reset, and explains why on page 23:
There is no reset metastability issue when reset is asserted because the reset signal bypasses the clock signal in a flip-flop circuit to cleanly force the output low
How can a asynchronous reset in a flip-flop be implemented such that asserting the reset carries no risk of metastability on the output?