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I have been working on this issue for a couple days and still cannot figure it out. I wonder if someone can help me with this.
You can just focus on the video process at the bottom of the code below. In each assignment line in this process, I have a comment "--input" or "--output" at the end.

Here is the problem:
- if I moved any line with the "--input" comment inside the "for 0 to 2 loop" and used the index as I did in the line "vid_fifos(i).clear_async <= aclear; --input" , the output of the FIFO is always undefined.

But if I put all the input assignments (all line with "--input" comment)outside the for loop as I did in those line above the for loop, it works fine, i.e. the FIFOs output valid data. This appears to be a problem with Modelsim only as the design works fine when I tested it on the Intel FPGA development board.
I appreciate if someone has any explanation for this.

The design is scalable and I need to put all the lines with "--input" comment inside the for loop and change the loop size. Thank you,

library ieee;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all;
ENTITY TEST1 is 
    port (  clk                 : in    std_logic;  
        reset                   : in    std_logic;                      
        pixels_in                   : in    std_logic_vector (0 to 47);
        pixels_out              : out   std_logic_vector (0 to 47);
        test_read               : in    std_logic;
        test_write              : in    std_logic;
        aclear                  : in    std_logic;
        sclear                  : in    std_logic;
        full                    : out   std_logic_vector(2 downto 0);
        empty                   : out   std_logic_vector(2 downto 0);
        words                   : out   std_logic_vector(29 downto 0)
        );
END;
ARCHITECTURE rtl of TEST1 is
type VID_FIFO is record
        data_in         : unsigned(15 downto 0);
        write           : std_logic;
        read            : std_logic;
        clear_async     : std_logic; 
        clock           : std_logic;  
        clear_sync      : std_logic;
        data_out        : std_logic_vector (15 downto 0);
        num_words       : std_logic_vector (9 downto 0);
        full            : std_logic ;
        empty           : std_logic;
    end record;
    type VID_FIFO_ARRAY is array (natural range <>) of VID_FIFO;
    signal      vid_fifos               : VID_FIFO_ARRAY(0 to 2);
    signal  test1 : std_logic :='0';
    --signal    cnt : unsigned(3 downto 0);
BEGIN
        G1: for i in 0 to 2 generate
          VIDEO_BUFFER: entity work.Fifo_x16_fifo_181_cdbx3jq port map (
            data    => std_logic_vector(vid_fifos(i).data_in), 
            wrreq   => vid_fifos(i).write,
            rdreq   => vid_fifos(i).read,
            clock   => vid_fifos(i).clock,
            aclr    => vid_fifos(i).clear_async,
            sclr    => vid_fifos(i).clear_sync,
            q   => vid_fifos(i).data_out,
            usedw   => vid_fifos(i).num_words,
            full    => vid_fifos(i).full,
            empty   => vid_fifos(i).empty
        );
    end generate;
VIDEO: PROCESS (all)  -- at least the clock changes, so this process shoudl be evaluate every clock
    Begin
            --vid_fifos(0).clear_async <= aclear; --input
            vid_fifos(0).clear_sync <= sclear;  --input
            --vid_fifos(1).clear_async <= aclear; --input
            vid_fifos(1).clear_sync <= sclear;  --input
            --vid_fifos(2).clear_async <= aclear;  --input
            vid_fifos(2).clear_sync <= sclear;  --input
            vid_fifos(0).clock <= clk;  --input
            vid_fifos(1).clock <= clk;  --input
            vid_fifos(2).clock <= clk;  --input
            vid_fifos(0).write <= test_write;  --input
            vid_fifos(1).write <= test_write;  --input
            vid_fifos(2).write <= test_write;  --input
            vid_fifos(0).read <= test_read;  --input
            vid_fifos(1).read <= test_read;  --input
            vid_fifos(2).read <= test_read;  --input
            vid_fifos(0).data_in <= unsigned(pixels_in(0 to 15));  --input
            vid_fifos(1).data_in <= unsigned(pixels_in(16 to 31));  --input
            vid_fifos(2).data_in <= unsigned(pixels_in(32 to 47));  --input
        for i in 0 to 2 loop   
            vid_fifos(i).clear_async <= aclear; --input
            full(i)     <= vid_fifos(i).full;  --output 
            empty(i)    <= vid_fifos(i).empty;  --output 
            words((i*10 +9) downto i*10) <= vid_fifos(i).num_words;  --output 
            pixels_out(i*16 to (i*16 + 15)) <= vid_fifos(i).data_out;  --output 
        end loop;   
    END PROCESS VIDEO;
END ARCHITECTURE;
\$\endgroup\$
  • \$\begingroup\$ I'm not able to reproduce this issue (admittedly with slightly different code). Which version of Modelsim are you using? Do you get the same problem if you explicitly expand your sensitivity list? \$\endgroup\$ – DonFusili Nov 30 '18 at 8:24
  • \$\begingroup\$ I am using ModelSim-DE 10.6e and yes i see the same problem when I explicitly expand the sensitivity list. \$\endgroup\$ – Dinh Nguyen Nov 30 '18 at 17:04
  • \$\begingroup\$ Did you come right with this? It's possible modelsim doesn't like custom types. Why not just drive the signals asynchronously in a generate statement? \$\endgroup\$ – stanri Feb 6 at 6:04

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