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Why do the two netlists give totally different output impedance values ?

netlist 1 run log

netlist 2 run log

Netlist 1:

*CMOS inverter https://electronics.stackexchange.com/questions/383552/measurement-of-output-impedance-of-a-cmos-inverter
.PARAM V_SUPPLY = 3.3
.PARAM AC_POINTS = 10
.PARAM AC_START = 1000
.PARAM AC_STOP = 1E6
VDD VDD 0 'V_SUPPLY'
VSS VSS 0 0
MP OUT IN VDD VDD P1 W='9.987275E-06' L=3.500000E-07
MN OUT IN VSS VSS N1 W='9.987275E-06/2' L=3.500000E-07 
CIN IN VSS 1E9
Rf OUT IN 1E9
IOUT VSS OUT AC 1
.AC dec 'AC_POINTS' 'AC_START' 'AC_STOP'
.OPTION POST PROBE ACCURATE
.include modelcard.nmos
.include modelcard.pmos
.MEASURE AC Zac_power0 rms par('abs(i(vdd))*v(vdd)')
.measure AC ZROUT1 rms par('v(OUT)/abs(i(VSS))')
.end

Netlist 2:

*CMOS inverter https://electronics.stackexchange.com/questions/383552/measurement-of-output-impedance-of-a-cmos-inverter
.PARAM V_SUPPLY = 3.3
.PARAM AC_POINTS = 10
.PARAM AC_START = 1000
.PARAM AC_STOP = 1E6
VDD VDD 0 'V_SUPPLY'
VSS VSS 0 0
MP OUT IN VDD VDD P1 W='9.987275E-06' L=3.500000E-07
MN OUT IN VSS VSS N1 W='9.987275E-06/2' L=3.500000E-07
CIN IN VSS 1E9
Rf OUT IN 1E9
IOUT VSS OUT AC 1
.OPTION POST PROBE ACCURATE
.include modelcard.nmos
.include modelcard.pmos
.control
*AC dec 'AC_POINTS' 'AC_START' 'AC_STOP'
AC dec 10 1000 1E6

let ROUT=OUT/abs(i(VSS))
plot ROUT
print ROUT > ROUT.log
.endc

.END

For exact problem duplication, just copy the two netlists into two different files and run ngspice. Cross-check the terminal output with mine as shown above.

The modelcard.pmos and model.nmos can be found at https://github.com/promach/frequency_trap/blob/development/optimization/inv

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  • \$\begingroup\$ Netlist 2 doesn't have a proper analysis statement. \$\endgroup\$ – HKOB Nov 30 '18 at 7:30
  • \$\begingroup\$ @HKOB Someone told me "meaning of RMS (root - mean - square), which is defined for real t,y tuples (values sampled at time points), when we apply it to a list of complex values where 'time' is another list of complex values". However, In this case, how should I modify .measure AC ZROUT1 rms par('v(OUT)/abs(i(VSS))') in order to avoid involving 'time' values in the ZROUT1 result computation ? \$\endgroup\$ – kevin Nov 30 '18 at 7:38
  • \$\begingroup\$ @HKOB Netlist 2 is from electronics.stackexchange.com/questions/383552/… which gives correct spice simulation output relative to theoretical calculation. Pleasee see carefully the link. Why netlist 2 does not have proper analysis statement ? \$\endgroup\$ – kevin Nov 30 '18 at 7:40
  • 1
    \$\begingroup\$ The difference between the two is the dot AC and .AC. I don't really have ngspice experience - maybe it accepts both. In the logs only one of the runs shows an ac analysis simulation. \$\endgroup\$ – HKOB Nov 30 '18 at 8:19
  • \$\begingroup\$ With the only AC source being the output load current you only need to plot V(out) to get Zout (if Ac magnitude = 1). Take the magnitude of Zout near DC to find Rout \$\endgroup\$ – HKOB Nov 30 '18 at 8:28

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