I am trying to solve question 11.10 which is taken from 2001 GATE IN paper.
So I think the answer is (a) because the input buffer which faces the analog input needs a higher slew rate in order to have a high bandwidth and acquisition time. While bias current St the output buffer will cause the hold capacitor to leak faster, so that needs to be minimised. Am I missing any other reason? I'd appreciate an detailed explanation on how slew rate affects the performance of this circuit.