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I am trying to solve question 11.10 which is taken from 2001 GATE IN paper.

question 11.10

So I think the answer is (a) because the input buffer which faces the analog input needs a higher slew rate in order to have a high bandwidth and acquisition time. While bias current St the output buffer will cause the hold capacitor to leak faster, so that needs to be minimised. Am I missing any other reason? I'd appreciate an detailed explanation on how slew rate affects the performance of this circuit.

circuit diagram

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    \$\begingroup\$ It sounds the right answer and for the reasons you give. \$\endgroup\$ – Andy aka Nov 30 '18 at 12:06
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    \$\begingroup\$ That's a perfectly good explanation. Keep in mind, though, that the some S/Hs require pretty good slew rates on the output buffer. If the sample and hold periods are fairly close, and the sample period is close to the settling time of the input buffer, the output buffer needs to be fast. The classic example of this is video DACs, where a S/H follows a very fast DAC, but the output needs to last only one pixel time. \$\endgroup\$ – WhatRoughBeast Nov 30 '18 at 13:11

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