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i am struggling on calculating the tpdhl / tplh i dont know how to calculate is there any algorethim for the way we calculate the time propagation high to low etc.. several questions asking to take the long path / short path but i really dont understand

for example enter image description here the full adder with 3 nand gates and 2 xor gate . seeing a soultion for this example will sure be really really helpful.

( you can choose random time for each gate just for the concept thank you again ! )

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  • \$\begingroup\$ Choose 1 input for consideration; choose one relevant output for consideration; add up the delays. Simple as that. \$\endgroup\$ – Andy aka Nov 30 '18 at 18:37
  • \$\begingroup\$ As @Andyaka says it is simple but the propagation delay depends on the logic family, individual gates and driving load. A NAND is typically faster than an XOR. \$\endgroup\$ – StainlessSteelRat Nov 30 '18 at 18:50
  • \$\begingroup\$ the lecturer used to write 0->1 or 1->0 in each wire of the gate can you explain whats the meaning of that why does he do such a thing ? \$\endgroup\$ – Razi Awad Nov 30 '18 at 19:37
  • \$\begingroup\$ Rising or falling. \$\endgroup\$ – Andy aka Nov 30 '18 at 21:42
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Using typical low fanout delays: 74LS00 74LS86

Propagation Delays

Assuming all gates transition.

C_OUT_PLH = 6.5 + 9 + 10 = 25.5ns typical

SUM_PHL = 6.5 + 7 = 13.5ns typical

SUM is two delays, while C_OUT is three delays.

I leave it to you to find the C_OUT_PHL and SUM_PLH. Pick a combination of A, B and C_IN to cause the NAND [5] to transition from H to L.

Longest involves 3 gate delays. Shortest involves 1 gate delay. SUM when C_IN changes.

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  • \$\begingroup\$ the lecturer used to write 0->1 or 1->0 in each wire of the gate can you explain whats the meaning of that why does he do such a thing ? \$\endgroup\$ – Razi Awad Nov 30 '18 at 19:37
  • \$\begingroup\$ also is this path only for the tpdHL ? because in other comments above one said that tpdlh is from C_IN to SUM \$\endgroup\$ – Razi Awad Nov 30 '18 at 19:39
  • \$\begingroup\$ one more thing if i have complicated circuit do i have to calculate every possible in put output with the tdhl / tpdlh or there is faster thing \$\endgroup\$ – Razi Awad Dec 1 '18 at 9:15
  • \$\begingroup\$ You have to look for the longest/shortest path and then figure out how to cause a transition along this path. This will involve a truthtable and walking 1's and 0's through the circuit. I'd do it in pencil and use a colored pen when I was happy with my choice. I'd mark up circuit as above with the addition of shortest path. \$\endgroup\$ – StainlessSteelRat Dec 1 '18 at 18:04
  • \$\begingroup\$ why did you calculate 2 gates in tpdlh ( Gate 1 , Gate 4 ) it should be only gate 4 right ? because its the shortest path to the sum or am i missing something \$\endgroup\$ – Razi Awad Dec 2 '18 at 21:15
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Assuming all gates have the same delay, (but the 2 types will have different delays), then the shortest time from High to Low, or Low to High, will be from C_IN to SUM, as it only goes thru gate 4. The longest time will be A or B to Cout when C_IN is involved, as gates 1, 2, and 4 are involved.

Both require the assumption that the other inputs are in the correct level to allow the signal of interest to pass thru without waiting for the other states to change.

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  • \$\begingroup\$ 1,2 and 5 \$\endgroup\$ – StainlessSteelRat Nov 30 '18 at 19:13
  • \$\begingroup\$ Yes, 5, my typo there. \$\endgroup\$ – CrossRoads Nov 30 '18 at 19:16
  • \$\begingroup\$ the lecturer used to write 0->1 or 1->0 in each wire of the gate can you explain whats the meaning of that why does he do such a thing ? \$\endgroup\$ – Razi Awad Nov 30 '18 at 19:37

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