Overflow detection and efficiency

I know the add instruction in mips32 will do overflow detection, i.e. add $t0,$s0, $s1; I want to know whether this feature will make it slower than addu$t0, $s0,$s1, which won't detection overflow.

Clarification:

1. For make anything faster: I assume that overflow detection in done by hardware. Then I want to know the hardware components itself for add, addu which is faster.

2. For Which implementation: The book I read mention about R2000, but think the solution is an general hardware design principle, which should not be restricted to a specific version. (i.e. I think there should be some requirement that clearly state whether it should cause delay.)

• How does the ALU generate an overflow signal? Does an Interrupt get generated? Or is a Test Instruction inserted into the binary-executable stream? – analogsystemsrf Dec 1 '18 at 9:58
• Clarify what you mean by "make anything faster". Faster in existing implementations? Or in a theoretical implementation of addu in an ALU that doesn't support add? Or on the pipelined execution of a sequence of instructions (that could depend on overflow)? These are very different questions. – Wouter van Ooijen Dec 1 '18 at 11:51
• Good explanation of MIPS overflow at Stack overflow: stackoverflow.com/questions/48619934/… – Peter Smith Dec 1 '18 at 11:53
• @WoutervanOoijen: Thank you for pointing out sir, I want existing implementations version. – Kindred Dec 1 '18 at 12:10
• Which implementation? – Wouter van Ooijen Dec 1 '18 at 12:19

The overflow logic is just hard wired; however, the update of the flag is ignored for addu instruction. The last bit just sets the update condition.
add: 0000 00ss ssst tttt dddd d000 0010 0000

There's virtually no speed difference between them. Also, considering that the MIPS is a synchronous processor and you clock at the rate of the slowest instruction, that add in any form will not cause you much speed concerns.