My architecture details

  • FPGA Implementation

  • Floating-pt format (IEEE 754)

  • At least 17 to 18 arithmetic operations (adders and multipliers) involved.

  • Currently instantiating the floating-pt IPs of multipliers (ALTFP_MUL) and adders (ALTFP_add_sub).

I was wondering if it's possible to infer these floating-pt multipliers and adders the way I can do for fixed-pt implementation!

By infer, I mean directly writing equation e.g. y <= a*b; rather than writing verbose port-mapping text.

I use VHDL. The design has to be synthesizable.


In a fixed-pt implementation, it was easy with some type casting and data-type conversion

e.g.y <= signed(a) * signed(b);

If possible, it will help me immensely in the development and I would be able to focus more on functionality.

  • \$\begingroup\$ You could use HLS instead of direct implementation. \$\endgroup\$ – M KS Dec 1 '18 at 16:36
  • \$\begingroup\$ @MKS As far as I know, you are talking about High level synthesis of Xilinx design flow. I'm working on Intel FPGA. Can you help with that? Any equivalent or relevance stuff for it? \$\endgroup\$ – Sourabh Tapas Dec 1 '18 at 17:24
  • \$\begingroup\$ I'm just working with Xilinx. For Intel, you should read their manuals. \$\endgroup\$ – M KS Dec 1 '18 at 18:51
  • \$\begingroup\$ You could use a binary numerical type such as found in -2008 package float_pkg. The only obvious difference between using a scalar floating point type (e.g. real) would be the lack of type inference between literals of type universal_real and a float type (see float_generic_pkg). You'd require explicit conversion routine calls, the composite float types are not closely related to type universal_real. (The -2008 float packages are synthesis eligible, and supported by some synthesis tools in earlier revisions as well as -2008). \$\endgroup\$ – user8352 Dec 2 '18 at 16:03

It depends entirely on how clever your synthesis tools might be, but I doubt very much that you can infer floating point operators. By the way, you could have tried this in less time than it took you to post the question.

  • \$\begingroup\$ I didn't get what do you mean by "tried this". How to instruct the tool that 'a' multiplied with 'b' are single precision data in IEEE 754 format and not a two's complement format. Just simply you can't multiply using * operator (If this is what you meant by "tried this"). Results won't be correct as IEEE 754 format has sign bit, exp and mantissa. You meant anything else then please elaborate what can I try. \$\endgroup\$ – Sourabh Tapas Dec 1 '18 at 17:22
  • 1
    \$\begingroup\$ I meant that you should declare a, b, and y to be type real and see what the synthesizer does with y <= a * b; \$\endgroup\$ – Elliot Alderson Dec 1 '18 at 17:48
  • \$\begingroup\$ real data type is not synthesizable. \$\endgroup\$ – Sourabh Tapas Dec 2 '18 at 5:20
  • 2
    \$\begingroup\$ And you just answered your own question. \$\endgroup\$ – Elliot Alderson Dec 2 '18 at 12:46
  • \$\begingroup\$ Thanks for your inputs. But I didn't ask the question to find out that real data type is synthesizable or not. I knew that beforehand that's why I had mentioned explicitly in question description itself ( "The design has to be synthesizable"). The aim of asking a question is to know that Is there any attribute or coding construct of which I'm unaware of? By which I can infer floating pt multiplication of two IEEE754 format data. Right now I'm doing it by instantiating the IP. If you mean NO to this then I can take it as your answer. \$\endgroup\$ – Sourabh Tapas Dec 4 '18 at 9:06

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