My architecture details
Floating-pt format (IEEE 754)
At least 17 to 18 arithmetic operations (adders and multipliers) involved.
Currently instantiating the floating-pt IPs of multipliers (ALTFP_MUL) and adders (ALTFP_add_sub).
I was wondering if it's possible to infer these floating-pt multipliers and adders the way I can do for fixed-pt implementation!
By infer, I mean directly writing equation e.g. y <= a*b; rather than writing verbose port-mapping text.
I use VHDL. The design has to be synthesizable.
In a fixed-pt implementation, it was easy with some type casting and data-type conversion
e.g.y <= signed(a) * signed(b);
If possible, it will help me immensely in the development and I would be able to focus more on functionality.