# Is it possible to infer a floating-pt multiplier in hdl coding without instantiating the IP?

My architecture details

• FPGA Implementation

• Floating-pt format (IEEE 754)

• At least 17 to 18 arithmetic operations (adders and multipliers) involved.

• Currently instantiating the floating-pt IPs of multipliers (ALTFP_MUL) and adders (ALTFP_add_sub).

I was wondering if it's possible to infer these floating-pt multipliers and adders the way I can do for fixed-pt implementation!

By infer, I mean directly writing equation e.g. y <= a*b; rather than writing verbose port-mapping text.

I use VHDL. The design has to be synthesizable.

PS:

In a fixed-pt implementation, it was easy with some type casting and data-type conversion

e.g.y <= signed(a) * signed(b);

If possible, it will help me immensely in the development and I would be able to focus more on functionality.

• You could use HLS instead of direct implementation. – M KS Dec 1 '18 at 16:36
• @MKS As far as I know, you are talking about High level synthesis of Xilinx design flow. I'm working on Intel FPGA. Can you help with that? Any equivalent or relevance stuff for it? – Sourabh Tapas Dec 1 '18 at 17:24
• I'm just working with Xilinx. For Intel, you should read their manuals. – M KS Dec 1 '18 at 18:51
• You could use a binary numerical type such as found in -2008 package float_pkg. The only obvious difference between using a scalar floating point type (e.g. real) would be the lack of type inference between literals of type universal_real and a float type (see float_generic_pkg). You'd require explicit conversion routine calls, the composite float types are not closely related to type universal_real. (The -2008 float packages are synthesis eligible, and supported by some synthesis tools in earlier revisions as well as -2008). – user8352 Dec 2 '18 at 16:03

• I meant that you should declare a, b, and y to be type real and see what the synthesizer does with y <= a * b; – Elliot Alderson Dec 1 '18 at 17:48