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Have anyone used this USB softcore before ?

Why do we need extra resistance on the tx pin ONLY ?

Whichever pins you transmit on need to have resistors after them. The exact values will depend on the internal resistance of the pins; usually something around 27 ohms will be ok.

According to section 7.1.1 (Tx) and 7.1.2 (Rx) of the USB 2.0 specification , it seems like we need some resistance for impedance matching for BOTH Tx and Rx.

enter image description here

1) is it correct that I only need TWO 27 ohm resistors in series (to compensate the low output impedance, say 73 ohm of FPGA pins) with the FPGA usbcorev softcore D+ and D- pins ?

2) And another 1.5 kilo-ohm pull-up resistor for D+ line ?

3) Since D+ and D- are bi-directional, do we need 15 kilo-ohm pull-down resistors for both D+ and D- line at FPGA pins ?

4) From on-chip termination section within intel cyclone IV IO inteface spec (have anyone used on chip termination ?) , I am not sure if I need to use external series termination resistors for both D+ and D- line. When I loop deeper into cyclone IV IO spec, it only supports 25 ohm or 50 ohm on-chip termination. This means this on-chip termination is not suffice for 90 ohm transmission line in USB spec . Could anyone advise ?

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  • \$\begingroup\$ signal integrity \$\endgroup\$ – JonRB Dec 1 '18 at 16:10
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First of all USB doesn't have a "TX pin" and an "RX pin" — both D+ and D- are used bidirectionally.

The reason for the series resistors (one on each pin) is that the output impedance of the FPGA pin drivers is significantly lower than the nominal impedance of the USB cable. A series resistor addresses this mismatch, eliminating signal reflections at that end of the connection.

This particular softcore uses two pairs of unidirectional pins to connect to the USB D+ and D- signals, rather than a single bidirectional pair. The termination resistors go between the Tx pair and the Rx pair, as follows:

schematic

simulate this circuit – Schematic created using CircuitLab

It isn't clear from the README.md file what additional logic is required for the rx_se0, tx_se0 and tx_en pins.

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  • \$\begingroup\$ First you say there's no TX and rx pins, then you show that this particular core does have separate TX and rx pins. \$\endgroup\$ – The Photon Dec 1 '18 at 18:17
  • \$\begingroup\$ @ThePhoton: The pins on the USB connector are bidirectional. \$\endgroup\$ – Dave Tweed Dec 1 '18 at 18:30
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    \$\begingroup\$ Technically configuring Tx outputs as tri-stated CMOS3.3 with 6 mA drive strength should give a decent 50-Ohm impedance match, so no resistors might be needed. \$\endgroup\$ – Ale..chenski Dec 3 '18 at 7:21
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    \$\begingroup\$ @kevin998x, no, you need to take a difference between Vcc and Voh, see here, electronics.stackexchange.com/a/402819/117785 \$\endgroup\$ – Ale..chenski Jan 6 at 3:44
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    \$\begingroup\$ @kevin, FPGAs don't have differential drivers that meet USB specifications. So the softcore uses available resources and makes the driver from two single-ended I/Os. \$\endgroup\$ – Ale..chenski Jan 7 at 17:26
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Dave Tweed has answered your original question. I am trying to address your additional ones:

1) is it correct that I only need TWO 27 ohm resistors in series (to compensate the low output impedance, say 73 ohm of FPGA pins) with the FPGA usbcorev softcore D+ and D- pins ?

You need in-series resistors only on Tx lines and only if you fail to configure the driver I/O to a better impedance match. Configuring I/O cells for 4 or 6 mA drive strength will give you a sufficiently good match, so no resistors might be necessary.

2) And another 1.5 kilo-ohm pull-up resistor for D+ line ?

Not exactly. The 1.5k pull-up on D+ line must be controlled from a different GPIO, and only when yet another GPIO senses the presence of VBUS coming in. Some USB PHY implementations disconnect the pull-up when transmitting, and connect it back to provide valid USB idle state of the bus.

3) Since D+ and D- are bi-directional, do we need 15 kilo-ohm pull-down resistors for both D+ and D- line at FPGA pins ?

No. 15k pull-downs must be (and will be) provided from host side of the link.

4) From on-chip termination section within INTEL cyclone IV IO interface spec (have anyone used on chip termination ?) , I am not sure if I need to use external series termination resistors for both D+ and D- line.

You can use the variable termination control using the mode with external calibration resistors, so you can set the impedance to nearly any value you need, this is both in Altera and Xilinx modern devices. But this is a hardware option, and your board must implement it and waste two pins form a bank. If you have some inexpensive development FPGA kit, it is very likely that footprints for this calibration resistors are not implemented. But the individual configuration for LVCMOS3.3V at 6 mA always remain as an option.

All-in-all, the FS mode of operation is not that sensitive to minor mismatches in transmission line impedance, so all this topic is just a nitpicking.

And no, you don't need 90-Ohm termination on receiver end for FS signaling interface, the receiver in FS mode is high-impedance receiver (open end).

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  • \$\begingroup\$ individual configuration for LVCMOS3.3V at 6 mA always remain as an option. <-- From intel.cn/content/dam/altera-www/global/zh_CN/pdfs/literature/hb/… , 6mA is not an option, only 2mA is supported \$\endgroup\$ – kevin Jan 7 at 4:53
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    \$\begingroup\$ @kevin, "6mA is not an option, only 2mA is supported" - then use a better FPGA, from Xilinx for example. They have 4 and 8 mA options for LVCMOS3.3. \$\endgroup\$ – Ale..chenski Jan 7 at 5:09
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    \$\begingroup\$ @kevin, from your page: "The voltage source on the pull-up resistor must be derived from or controlled by the power supplied on the USB cable such that when VBUS is removed, the pull-up resistor does not supply current on the data line to which it is attached." \$\endgroup\$ – Ale..chenski Jan 7 at 7:36
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    \$\begingroup\$ @kevin, it would be called "derived from VBUS". Passive "deriving" from VBUS has a lot of problems. If the divider has low resistance and "equivalent" pull-up meets the minimum relaxation time of 2.5 us, the device will likely fail the suspend current limit. If the divider has high-value resistors, it may fail either 2.5 us, or 15k pull-downs on host side will lead to invalid pull-up level. I recommend the pull-up to be "controlled". \$\endgroup\$ – Ale..chenski Jan 7 at 8:44
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    \$\begingroup\$ Having looked at the USB spec : full speed driver circuit , for Cyclone IV i.imgur.com/x8jaaaF.png , there's no calibrated series termination that matches the USB FS requirement of 28 - 44 ohm driver impedance. And how does this 28 - 44 ohm driver impedance relate to the 90 ohm transmission line ? \$\endgroup\$ – kevin998x Jan 8 at 1:36

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