I need to find a circuit that produces a rectangle wave(picture below) and that only uses one capacitor(0.01 micro Farad), 1 amp op with a single supply line(Vsat+ = +10V and Vsat- = 0) and how ever many resistors is needed. I can only use these elements. img This is what I have done till now:


For that, I want to use an relaxation oscillator because it produces a square wave but the problem is that because Vsat- is equal to zero, the capacitor won't discharge to 0 and I have researched a lot on the topic and can't find anything.

Your help would be greatly appreciated and sorry for my English it's not my first language.

  • \$\begingroup\$ I suggest looking at the internal circuit of the 555 timer and studying how it works. You might get some inspiration there, since it basically does exactly this. \$\endgroup\$ Dec 1, 2018 at 18:29
  • \$\begingroup\$ Initially I couldn't see how you can do that without adding at least one more non-linear element (a diode or transistor). However I realized that you can exploit the non-linearity of the op-amp and its relationship with the supply rails. \$\endgroup\$ Dec 1, 2018 at 18:36
  • \$\begingroup\$ @LosFrijoles, when I was making some research I saw links on the 555,the only problem was that it used some flip flop gates maybe I'm mistaken I'll look into it again thank you \$\endgroup\$
    – Tassarei
    Dec 1, 2018 at 18:55
  • \$\begingroup\$ @EdgarBrown Are you talking about the analysis to know the conditions of saturation and linearity ? I did it but my problem was Vsat- and R1/(R1+R2)*Vsat- were equal and I was a little lost, I don't know if it makes any sense \$\endgroup\$
    – Tassarei
    Dec 1, 2018 at 18:57
  • 1
    \$\begingroup\$ @Tassarei you are over-constraining your problem. Think of why do you really require the capacitor to discharge to zero? \$\endgroup\$ Dec 1, 2018 at 19:01

3 Answers 3



I hadn't really considered this before and now that I have thought a little further I think it's actually easier than I'd suggested in the comments. You could go with an added series resistance to the output, as I suggested. Or the approaches that have been also added here (an offshoot of what I was earlier thinking about.)

But it's not needed.

Basic idea

Here's the basic idea (I'm assuming you will use an rail-to-rail in/out opamp such as the LT1800, for example):


simulate this circuit – Schematic created using CircuitLab

To get a duty cycle of \$\frac13\$rd, you want the average (mean) current in \$R_4\$ to be twice as much when the output of the opamp is HIGH than when the output of the opamp is LOW. In effect, this means that the difference between the opamp's \$V_{\text{OUT}_\text{HIGH}}\$ and the average of \$V_{\text{H}_\text{LOW}}\$ and \$V_{\text{H}_\text{HIGH}}\$ must be twice as much as the difference between the opamp's \$V_{\text{OUT}_\text{LOW}}\$ and the average of \$V_{\text{H}_\text{LOW}}\$ and \$V_{\text{H}_\text{HIGH}}\$.



Since \$V_{\text{OUT}_\text{LOW}}=0\:\text{V}\$ and \$V_{\text{OUT}_\text{HIGH}}=V_\text{CC}\$ for any similar circuit, regardless of \$V_\text{CC}\$, it follows that:

$$V_{\text{H}_\text{LOW}}+V_{\text{H}_\text{HIGH}}=\frac23 \:V_\text{CC}$$

You also should be able to work out the following two equations:

$$\begin{align*} V_{\text{H}_\text{LOW}} &= V_\text{CC}\frac{R_2\:R_3}{R_1\:R_2+R_1\:R_3+R_2\:R_3}\\\\ V_{\text{H}_\text{HIGH}} &= V_\text{CC}\frac{R_2\:\left(R_1+R_3\right)}{R_1\:R_2+R_1\:R_3+R_2\:R_3} \end{align*}$$

Knowing all of the above, you could choose to specify \$R_3\$ and \$V_{\text{H}_\text{LOW}}\$ and then work out the details for the required values of \$R_1\$ and \$R_2\$ (and, obviously, the resulting \$V_{\text{H}_\text{HIGH}}\$, too.)


As some time has passed now, I'll provide some equations:

$$\begin{align*} R_1&=2\:R_3\cdot\frac{V_\text{CC} - 3\:V_{\text{H}_\text{LOW}}}{3\:V_{\text{H}_\text{LOW}}}\\\\ R_2&=2\:R_3\cdot\frac{V_\text{CC} - 3\:V_{\text{H}_\text{LOW}}}{V_\text{CC} + 3\:V_{\text{H}_\text{LOW}}}\\\\ V_{\text{H}_\text{HIGH}}&=\frac23\:V_\text{CC} - V_{\text{H}_\text{LOW}} \end{align*}$$

From these, it is easy to see that \$V_{\text{H}_\text{LOW}}\lt\frac{V_\text{CC}}{3}\$. So your choices for \$V_{\text{H}_\text{LOW}}\$ are constrained.


but the problem is that because Vsat- is equal to zero, the capacitor won't discharge to 0 and I have researched a lot on the topic and can't find anything.

Your problem is, as you say, the fact that the cap never discharges to zero. What you've missed is that all of the examples you've seen expect an op amp with both plus and minus power supply voltages, so Vsat- will be negative, which will discharge the cap below the - threshold voltage.

You can handle this two ways


simulate this circuit – Schematic created using CircuitLab

You can do R9 and R10 in either of two ways. First, as I've shown, make them much smaller than R8, or get select them so that their Thevenin equivalent resistance is equal to R8 and eliminate R8 altogether.


First of all, let me jump to the solution directly:

RC oscillator using op-amp based hysteric comparator

The schematic illustrates the topology of the oscillator. The only component added to your original network was R3. The value and op-amp I picked are kind of arbitrate since it is used to illustrate the idea. The plot the captured the waveform on Vout, V-, and V+.

Now, let take a closer look at the circuit and analyze how it works. The first thing to keep in mind is that this is NOT a negative feedback circuit. The virtual short/open, or feedback gain techniques won't apply here.

Take a look at the two networks below:


simulate this circuit – Schematic created using CircuitLab

The difference is the polarity of the op amp. The right side one is a gain-2 amplifier because it has negative feedback, while the left one is a comparator with hysteresis.

Since you want an oscillator, the left side circuit is what you need. Imagine Vin sweeps from low to high, at the very beginning, V- < V+ and V+ = Vdd*R1/(R1+R2). This is the rising edge threshold of the comparator.

Once Vin crosses this threshold, Vout of the op amp will drop to Vee, yielding V+ = Vee*R2/(R1+R2) (note that Vee is a negative value). This is the falling edge threshold.

If Vin starts to sweep from high to low, Vout won't change until Vin is lower than the falling edge threshold.

With this in mind, let's get back to the circuit in our solution. R1, R2, and R3 sets the rising and falling thresholds:

The rising threshold V_rise = Vdd* R1 / [R1 + (R3 // R2)] The falling threshold V_fall = Vdd* (R1//R2) / [R3 + (R1 // R2)] (This assumes the op amp is ideal and has rail-to-rail out swing)

Therefore V_rise > V_fall. In your original circuit, the R3 = +inf. (open circuit) V_fall = 0. Therefore, it can't oscillate.

The switching frequency can be adjusted by the RC time constant formed by R4 and C1. Pick R4 according to the op amp's driving capability and C1 according to the frequency.

Changing the ratio between R3 and R1 adjusts the duty cycle of the network. A larger R3/R1 will yield a larger duty circle. In your original circuit, R3/R1 = +inf. Therefore you duty circle is 100%, and the circuit failed to oscillate. That's another point of view to see why your circuit failed to operate.

One thing to keep in mind is that this network's oscillating frequency and duty cycle are not decoupled. That means every time you change R1, R2, and R3, you must change C1 again to get exact the previous frequency.

The low value limit of R1, R2, and R3 should be selected according to power consumption restrictions, while the high value limit are thermal noise.

To achieve good jitter performance, NP0 ceramic cap can be used for C1.

Finally, in real life, if op-amp's output is used as your clock output, it is unlikely (but not impossible) you will get rail-to-rail voltage swing. This can be easily solved by adding an inverter after Vout.

Also, the same oscillator can be achieved by replacing the op-amp and R1~R3 with a single schmitt trigger inverter: a much cheaper and a simpler solution.

I hope this answers your question.

  • \$\begingroup\$ Welcome to EE.SE. If you read the question and comments it becomes clear that this is homework so nobody has posted a complete answer even though it's clear that several of them can think of methods to solve the problem. Those commenting on the question were prompting the OP to work it out for her/himself. I think s/he has nearly got it now so you can let your answer stand. \$\endgroup\$
    – Transistor
    Dec 1, 2018 at 23:05
  • \$\begingroup\$ Thanks a lot for your guidance! I will be more careful. \$\endgroup\$
    – Yong Liao
    Dec 2, 2018 at 18:13

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