I'm planning to do a waveform generator using an FPGA board (spartan 6 board from diychips), however I am new to verilog so I am encountering a bit of a problem. I created a sine-wave sequence using MATLAB and imported it into my verilog code. Here's the code that should output the 7 bit sequence :
module dac7bit(input M_CLOCK, output reg [6:0] DAC); reg[8:0] counter; reg clk = 0; reg[4:0] i = 0; always @(posedge M_CLOCK) begin counter <= counter+1; if(counter==320)begin clk <= ~clk; counter <= 0; end end always @(posedge clk) begin case(i) 5'b00000 :DAC <= 7'b1000000; 5'b00001 :DAC <= 7'b1001111 ; 5'b00010 :DAC <= 7'b1011110 ; 5'b00011 :DAC <= 7'b1101011 ; 5'b00100 :DAC <= 7'b1110110 ; 5'b00101 :DAC <= 7'b1111100 ; 5'b00110 :DAC <= 7'b1111111 ; 5'b00111 :DAC <= 7'b1111110 ; 5'b01000 :DAC <= 7'b1111001 ; 5'b01001 :DAC <= 7'b1110001 ; 5'b01010 :DAC <= 7'b1100101 ; 5'b01011 :DAC <= 7'b1010111 ; 5'b01100 :DAC <= 7'b1001000 ; 5'b01101 :DAC <= 7'b0110111 ; 5'b01110 :DAC <= 7'b0101000 ; 5'b01111 :DAC <= 7'b0011010 ; 5'b10000 :DAC <= 7'b0001110 ; 5'b10001 :DAC <= 7'b0000110 ; 5'b10010 :DAC <= 7'b0000001 ; 5'b10011 :DAC <= 7'b0000000 ; 5'b10100 :DAC <= 7'b0000011 ; 5'b10101 :DAC <= 7'b0001001 ; 5'b10110 :DAC <= 7'b0010100 ; 5'b10111 :DAC <= 7'b0100001 ; 5'b11000 :DAC <= 7'b0110000; default: DAC <= 7'b0100000; endcase i<=i+1; if(i==24) begin i<=0; end end endmodule
I have created a register DAC that I have mapped in the .ucf file, using this datasheet. The pins are then connected to the R2R DAC outside the board via jumpers. I am not sure if this is the way to do it (to map the pins), I got this idea from how this was done for the I/O board shipped with the FPGA board itself. Here's the .ucf file:
# DAC NET "DAC<6>" LOC = P104; NET "DAC<5>" LOC = P101; NET "DAC<4>" LOC = P99; NET "DAC<3>" LOC = P97; NET "DAC<2>" LOC = P94; NET "DAC<1>" LOC = P92; NET "DAC<0>" LOC = P87; #==================================================== # Clock signal NET "M_CLOCK" LOC = P123;
However I could't probe anything, all of the pins were high. I thought that the problem might be with generating my own clock signal, or with the case() syntax, so I tried to just assign some 7 bit value to DAC register on each M_CLOCK cycle. Still, nothing has changed. Therefore I think that the problem is with either initializing the DAC register, mapping it, or assigning values to it, however I can't find anything that could help.
The problem was much more trivial than I expected. It was due to the software I was using. I had installed Xilinx ISE on a Windows 8 machine and some of the features (such as producing working bit .mcs files it would seem) were bugged. Once I got to my school computer that runs a working version of ISE the code worked as expected.