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CPU clocking involves making sure that each operation or part of an operation takes exactly a certain amount of time (the machine cycle time).

One way to increase the efficiency of a cpu is by introducing pipelining: we cut a basic computation (e.g. floating point multiplication) into parts, and then make sure that each part lasts one machine cycle. If we then have e.g. 5 parts, we can theoretically run 5 instructions simultaneously by having them go through each stage of the pipeline separately.

However, pipelining requires the use of latches, in order to demarcate the stages of the pipeline, and the cpu clock is connected to these latches. This puts an upper bound on the number of computations that can be performed simultaneously: at the very least, there cannot be more stages than the depth of the combinational circuit.

However, my thought is: get rid of clocking altogether, and get rid of the latches. Then simply send each computation “immediately after the other” So the circuit will theoretically be able to do as many computations such that signals immediately sent after each other are still distinguishable.

I know that this has many practical problems:

  • writing the results to memory will be a bottleneck (i think)

  • timing the computations is difficult.

Nevertheless, I am wondering whether such a proposal has any hope of ever being implemented? Have people worked on this already?

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    \$\begingroup\$ This is a current area of research, actually. It's called asynchronous computing. \$\endgroup\$ – Hearth Dec 3 '18 at 13:07
  • \$\begingroup\$ @Hearth, I was under the impression that asynchronous computing is something more general, namely including the case where two separate processes simultaneously run while being part of the same application, even if the processor that runs them is clocked. \$\endgroup\$ – user56834 Dec 3 '18 at 13:09
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    \$\begingroup\$ Asynchronous computing (particularly for FPGAs) has been an active research area for some years, but many serious problems have yet to be solved. \$\endgroup\$ – Peter Smith Dec 3 '18 at 13:13
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    \$\begingroup\$ This is rather like saying "we could all drive faster if we left no space between cars"; the gap is there for a reason. \$\endgroup\$ – pjc50 Dec 3 '18 at 13:31
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    \$\begingroup\$ I've seen partial asynchronous computing designs on FPGAs. Ironically, they're used in designs where there's a compute path which can take extremely long relative to the clocked processes so you put the inputs to the path in clock cycle 0 and only read the result multiple clock cycles later, when you're sure all race conditions and metastability has died out. It's horrible to synthesize and always only there because someone wanted to be special. Conversely, they get a special place in hell. \$\endgroup\$ – DonFusili Dec 3 '18 at 14:10
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The technique is called "wave pipelining" and it has been studied for fifty years. It is very difficult to achieve in practice so it has remained an arcane research topic. The difficulty is maintaining precise timing relationships between timing paths in the face of manufacturing variation, power supply variation, temperature variation, etc.

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Theoretically yes. It is called asynchronous logic and it has been considered for decades, particularly due to power distribution advantages. In principle every section of a process can be individually optimized and local handshake signals take care of the data flow. In some applications there can be large efficiency and speed gains, but the trade off becomes statistical performance measures instead of deterministic ones. This makes it harder to integrate in a design. Basically this leaves the detailed understanding of the design timing to the end user instead of addressing it up front.

However the advantages of fully asynchronous design have been mostly incorporated into mesochronous design, where the multiple sections of an IC run with different clock phases and speeds, but these still synchronize at the boundaries thus preserving global synchrony in the system and worst-case performance guarantees.

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Each stage of the process has to tell the next when it is ready: this is effectively a clock for the next stage.

It's true that the stages don't necessarily have to have the same clock as each other, but they have to have some way to say "here is my output". The clocks of serial-to-parallel convertors are often not directly related to the output clocks.

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There's something called Hazard (aka Race hazard), long story short, it's about the delays of each individual logic gates, one path from input to output may be faster than some other path. This in turn means that the output may very likely be wrong until all the inputs has propagated to the output.

A solution to the hazard is to use a clock and give enough time so whatever that is at the output is correct.

Another solution to the hazard is to look into the Karnaugh map (K-map) of your boolean function and make all groups (terms) overlap. You can't always overlap groups in the K-map, a solution to that sub-problem would be to add a "done" signal, which essentially would act as a clock. Also, adding more groups so all groups are connected leads to more gates which leads to more transistors and more power consumption and less space on the silicon for your circuit.

Let me rewrite it a little bit. Usually people use K-maps to find the smallest number of gates required to represent a boolean function, but we'd use it to find what to overlap, meaning we will probably not get a minimal solution. And whatever speed our circuit will work in, whatever the theoretical maximum actually is, we could instead use a clock for that along with a minimal solution.


If I'm not clear enough, yes, you can do it, go ahead. But you're most likely going to lose on it.

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