CPU clocking involves making sure that each operation or part of an operation takes exactly a certain amount of time (the machine cycle time).
One way to increase the efficiency of a cpu is by introducing pipelining: we cut a basic computation (e.g. floating point multiplication) into parts, and then make sure that each part lasts one machine cycle. If we then have e.g. 5 parts, we can theoretically run 5 instructions simultaneously by having them go through each stage of the pipeline separately.
However, pipelining requires the use of latches, in order to demarcate the stages of the pipeline, and the cpu clock is connected to these latches. This puts an upper bound on the number of computations that can be performed simultaneously: at the very least, there cannot be more stages than the depth of the combinational circuit.
However, my thought is: get rid of clocking altogether, and get rid of the latches. Then simply send each computation “immediately after the other” So the circuit will theoretically be able to do as many computations such that signals immediately sent after each other are still distinguishable.
I know that this has many practical problems:
writing the results to memory will be a bottleneck (i think)
timing the computations is difficult.
Nevertheless, I am wondering whether such a proposal has any hope of ever being implemented? Have people worked on this already?