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enter image description hereI have designed a custom USB hub PCB with a TI TUSB2046(USB Full-Spped hub).

Considering 12Mbps data rate, how critical are the layout constraints for the USB data lines?

I did not follow the exact layout guidelines (had a short stub, slight length mismatch etc, did not use a differential impedance calculator).

The hub gets enumerated on the host PC, but the downstream devices don't. Could the PCB layout have anything to do with this?

EDIT: I have attached the schematic.

enter image description here

EDIT: I have attached the Device manager screenshot.

enter image description here

Please enlighten, thanks.

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    \$\begingroup\$ How are power & Gnd connected to all the devices? I only see signal connections in your layout. \$\endgroup\$ – CrossRoads Dec 3 '18 at 17:07
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    \$\begingroup\$ Power is being supplied externally through the jumper pin connection on the bottom edge. The top layer polygon and bottom layer are Gnd. \$\endgroup\$ – Rohit Garg Dec 3 '18 at 17:10
  • \$\begingroup\$ Even if all of your USB devices are self-powered, you still need the VUSB connection to each one -- it's what kicks off the enumeration process. \$\endgroup\$ – Dave Tweed Dec 3 '18 at 18:59
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    \$\begingroup\$ If your devices, as well as your hub, are custom assemblies, then that's information you've been withholding. I think I'm done here. \$\endgroup\$ – Dave Tweed Dec 3 '18 at 19:56
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    \$\begingroup\$ I see a couple of potential issues. There are 2 devices on the D0 pair (one physical device per pair only), and the two lower devices are pulling both DP and DM down where the detection requires a pull-up on either DP or DM. See ftdichip.com/Support/Documents/TechnicalNotes/… \$\endgroup\$ – Peter Smith Dec 7 '18 at 13:11
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The PCB layout for USB Full-Speed is somewhat critical. It is more critical than the layout for a 400 kHz I2C bus, but not as critical as a 6 Gb/s SATA bus.

It is possible that you have layout issues that are preventing the downstream devices from enumerating. These "issues" might include, but not be limited to, proper layout of high speed signal paths. You might also have a problem with power distribution or bypassing. Maybe you installed the wrong resistor somewhere. Perhaps you have a bad solder joint on a connector.

You might want to try asking a more specific question and providing much more information if you need more detailed advice.

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  • \$\begingroup\$ My doubt was also that the hub by itself was getting enumerated. But downstream devices aren't. So does that isolate the issue to downstream data lines? \$\endgroup\$ – Rohit Garg Dec 3 '18 at 17:04
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Page 18 of the TUSB2046 datasheet says in section 11.1.3 that "The thermal pad of the TUSB2046x and any of the voltage regulators should be connected to this plane with vias." Based on your layout, it looks like the thermal pad is only connected to the GND plane through a few relatively thin traces. I suspect that this is part of your problem.

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  • \$\begingroup\$ I am using the LQFP package without the thermal pad. The islanded pad under the IC is actually a Vcc connection. \$\endgroup\$ – Rohit Garg Dec 3 '18 at 17:13
  • \$\begingroup\$ Ah. My mistake. \$\endgroup\$ – Chris Fernandez Dec 3 '18 at 17:23
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Its quite old thread but will add my two cents.

I have been designing several USB devices and haven't had any problems just by applying these easy to understand rules made by Intel. My personal experience is that is good to try comply with most of the requirements or you will be surprised at the latest in EMI testing... At least check them out.

(Sorry didn't find original sources):

High Speed USB Platform Design Guidelines http://apachetechnology.in/KC/Multimedia/PCI/hs_usb_pdg_r1_0.pdf

EMI Design Guidelines for USB Components https://www.ti.com/sc/docs/apps/msp/intrface/usb/emitest.pdf

Good luck!

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