I'd like to code a one-hot fsm in vhdl. I've done many in verilog but my current employer prefers vhdl. In verilog I'd use the "inverse case statement" (case 1'b1) to compare each bit in the state vector in parallel. Then with a parallel-case pragma, or a "unique" declaration in system verilog, we synthesize to the right result.
But... Vhdl doesn't seem to allow a reverse case statement. There's no need for parallel_case since case is always parallel in vhdl. The best example I found, from Steve Golson's paper (in 1994!) uses cascaded if statements. There's no "else" but it seems to me these should become priority encoders and not parallel state checking. So I'm kind of at a loss.
Asking co-workers won't help, nobody uses this coding style and I'm trying to show them how well it works. But maybe there's a reason these vhdl guys don't use it...