I'm placing bypass capacitors underneath a BGA package. In some cases the caps cannot land directly on the vias-in-pad ("VIP"), so I'll need short traces from the VIPs to the caps:


In this example image, the cap is 0201 (0603 metric) and the BGA has 0.4mm spacing. The VIPs are 6-mil (0.15mm) holes filled with conductive material. In the actual design, I'll have wider connections between the VIPs and the capacitor than shown here.

However, this causes the following problem: The BGA balls are connected to the power/ground planes through the inductance of the VIPs, and then there is additional inductance (the other half of the VIPs) between the planes and the cap on the other side. My concern is that the capacitor won't actually accomplish much, since any noise will hit the planes first and will be partially isolated from the capacitor.

A possible solution is to run the VIPs through the PCB without having them contact the power planes, then to the caps, and place an additional set of VIPs (to the power planes) on the capacitor pads. But then I've really increased my loop area, which I obviously don't want to do.

Are these valid concerns? What are the best practices here?

  • \$\begingroup\$ Why can’t you have vias in pad for the capacitors themselves connecting directly to the planes? You want to minimize your inductance between the caps and the planes in order to provide a low impedance path to ground. Do you have access to FEM tools (SIWave, ANSYS)? If you are worried about such things you need to carry out power integrity analysis with such tools. What is the frequency of operation of the IC? Analog or digital? What about internal circuits in the IC that run at a faster clock rate? \$\endgroup\$ – user110971 Dec 4 '18 at 21:46
  • \$\begingroup\$ @user110971 In some cases I can place the capacitor's pads directly underneath the BGA's balls, and use a through-VIP to connect everything together. In some cases it doesn't line up so I'll need to offset the caps. I don't have access to such tools now, so I'm trying for "best practices". I have a few different IC's, primarily digital, with local clocks at 25-72Mhz, in addition to a 2.4Ghz narrow-band and a 3.5GHz ultra-wide-band transceiver. \$\endgroup\$ – bitsmack Dec 4 '18 at 22:32
  • 1
    \$\begingroup\$ In that case the best you can do is to have a pair of VIPs connecting the BGA pin to power / ground and an additional pair of VIPs connecting the capacitor to power / ground. It would be preferable, If you can get at least one capacitor pad to line up with one of the BGA VIPs. Then you rotate the capacitor such that the other pad is as close as possible to the other BGA VIP and place a third VIP in that capacitor pad to power / ground. \$\endgroup\$ – user110971 Dec 4 '18 at 23:17

The ESL for an 0201 capacitor looks like this:

enter image description here

Source: https://ds.murata.co.jp/simsurfing/mlcc.html?lcid=en-us#

The inductance for a 5mil via is about 1.546nH

enter image description here
Source: http://www.saturnpcb.com/pcb_toolkit/

So the ESL of the capacitor is being reduced significantly by the vias, however, with a BGA part we can't put the capacitor next to the part so, a capacitor is better than nothing at all. If we look at the circuit we would like to use the one on the right below, but since the BGA will get in the way we place vias on the opposite side of the board and deal with the inductance. Bigger vias have lower inductance. If there is a significant worry for noise and a way to parallel the vias, then paralleling the vias could minimize inductance.


simulate this circuit – Schematic created using CircuitLab


The caps will definitely help. The plane is a low impedance conductor, but it still has impedance, and the larger the distance a pulse propagates, the more destructive it becomes. I've had good results using large feedthrough caps for bypass due to their extremely low inductance and multiple attachment paths.


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